PST Validation Engineer - San Diego, California, United States of America
$98,500 - $147,700 USD yearly
Originally posted 29 May 2026 by the employer.
About the role
As a PST Validation Engineer in ASICS Engineering, you will handle post-silicon validation and emulation across system-level PVTs and SoC IPs.
What you'll do
- Perform silicon bring-up, measure post-Si Vmin/Fmax, power, and thermal data, and correlate, characterize, and analyze at the system level across various PVTs and SoC IPs. - Debug low-level software and hardware issues using debug tools such as JTAG and kernel debuggers. - Manage emulation builds, run tests, identify failures and performance issues, and collaborate with CAD, RTL, and Design teams to resolve them. - Automate validation flows, data collection, and analysis using Python or similar scripting languages.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2 years of ASIC design, verification, validation, integration, or related work experience (or Master's degree with 1 year of experience, or PhD). - Understanding of mobile chip architecture (CPU, GPU, DDR, NOCs), basic RTL, and transistor power fundamentals. - Knowledge of regression and PVT (Process, Voltage, Temperature) testing, including data analysis and extraction of key metrics. - Experience debugging low-level software and hardware issues using tools like JTAG and kernel debuggers (such as Lauterbach Trace32). - Programming and scripting skills in C and Python. - Experience architecting and developing test bench infrastructure for CPU/SoC emulation across different platforms.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. - 6 months of experience with architecture and design tools. - 6 months of experience with scripting tools and programming languages. - 6 months of experience with design verification methods.
Skills: Silicon bring-up, Post-Si Vmin/Fmax, Power, thermal data, debug low-level software and hardware, JTAG
This role has been open 147 days — well above the 40-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
432
|
Median days open
40 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (432 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 38 | 432 |
| Open roles in the wider Silicon Validation & Test family | 138 | 2238 · 112 employers |
| Median days open | 30 d | 40 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: Silicon bring-up, Post-Si Vmin/Fmax, Power, thermal data, debug low-level software and hardware, JTAG
Who's hiring in this category
- AMD · 54 open roles · median 43 d
- Qualcomm (this employer) · 38 open roles · median 30 d
- Micron Technology · 36 open roles · median 39 d
- NVIDIA · 26 open roles · median 25 d
- Microchip Technology · 22 open roles · median 75 d
- Apple · 20 open roles · median 2 d
How we counted: 432 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.