Product Technical Chip Lead, Senior Director - San Jose, California, United States
$260,000 - $295,000 USD yearly
Originally posted 9 April 2026 by the employer.
Drive execution for 300-400mm² chips utilizing 2.5D/3D advanced packaging and UALink, UCIe, and PCIe Gen6/Gen7 technologies.
About the role
Astera Labs is seeking a Product Technical Lead (Chip Lead), Senior Director to drive execution and technical ownership across the lifecycle of UALink switching products in San Jose. The role integrates architecture, design, validation, firmware, systems, and operations on devices incorporating UALink, UCIe, and PCIe Gen6/Gen7 technologies.
What you'll do
- Own the full technical lifecycle of switching products from architecture assumptions through design integration, validation strategy, and tapeout signoff. - Drive chip development execution from RTL to GDSII, ensuring implementation and tapeout milestones are achieved. - Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures. - Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria. - Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies. - Work with physical design teams on timing closure, power optimization, and backend execution.
What you'll need
- Experience driving chip development execution from RTL to GDSII and managing chip tapeout and signoff. - Technical background in large-scale chips (300-400mm²) incorporating 2.5D/3D advanced packaging technologies and chiplet-based architectures. - Deep expertise across high-speed interconnect protocols including UALink, UCIe, and PCIe Gen6/Gen7. - Demonstrated experience defining validation strategies, coverage goals, regression plans, and silicon sign-off criteria. - Technical understanding of DFT strategies, including test architecture, scan insertion, BIST, and manufacturing test. - Hands-on knowledge of physical design processes including timing closure and power optimization.
Skills: UALink switching, chip development, RTL to GDSII, chiplet-based architectures, validation strategy
This role has been open 198 days — well above the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
477
|
Median days open
79 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (477 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 477 |
| Open roles in the wider Digital Design & Verification family | 59 | 3310 · 115 employers |
| Median days open | 112 d | 79 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: UALink switching, chip development, RTL to GDSII, chiplet-based architectures, validation strategy
Who's hiring in this category
- Qualcomm · 80 open roles · median 83 d
- NVIDIA · 56 open roles · median 67 d
- Apple · 37 open roles · median 17 d
- AMD · 36 open roles · median 74 d
- Arm Holdings · 27 open roles · median 122 d
- Micron Technology · 21 open roles · median 101 d
How we counted: 477 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.