Product Engineering Architect - San Jose, United States
$185,500 - $344,500 USD yearly
Originally posted 24 September 2026 by the employer.
About the role
This Product Engineering Architect role provides senior technical leadership for the development and proliferation of Cadence Virtuoso Heterogeneous Integration technologies. It shapes the product roadmap for physical implementation flows around 3D IC, heterogeneous integration, and advanced packaging.
What you'll do
- Drive, validate, and promote end-to-end solutions for system design implementation flows.
- Lead strategic customer engagements for advanced heterogeneous integration and multi-die co-design methodologies.
- Influence product roadmap direction by synthesizing customer requirements, market trends, and technical feasibility.
- Produce high-quality Product Requirement Specifications (PRS) and technical use cases.
- Provide technical leadership for requirement trade-off analysis and solution validation.
- Mentor and guide product engineers on complex design-flow challenges and technical decision-making.
What you'll need
- BS in Electrical Engineering, Electronics, or a related technical field.
- Deep expertise in semiconductor design, physical implementation, advanced packaging, or EDA product engineering.
- Strong hands-on knowledge of the Cadence Virtuoso platform and associated custom IC design flows.
- 15+ years of relevant experience in product engineering, methodology development, customer enablement, or technical leadership roles.
- Demonstrated ability to shape technical direction and align cross-functional stakeholders.
- Proven track record working with strategic customers, including executive-level technical communication and successful deployment of advanced design flows.
Nice to have
- Experience with co-design flows around 3D IC, heterogeneous integration, and silicon-package-board integration.
- Knowledge of Cadence Allegro Package Designer Plus (APD+) and package implementation methodologies.
- Knowledge of Cadence Virtuoso SKILL language or any other interpreted language.
Skills: 3D IC, heterogeneous integration, advanced packaging, Cadence Virtuoso platform, design implementation flows, product roadmap
This role has been open 0 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
85 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (683 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 172 | 683 |
| Open roles in the wider Physical Implementation family | 203 | 1417 · 108 employers |
| Median days open | 147 d | 85 d (+62 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Skills observed across this category: 3D IC, heterogeneous integration, advanced packaging, Cadence Virtuoso platform, design implementation flows, product roadmap
Who's hiring in this category
- Cadence Design Systems (this employer) · 171 open roles · median 147 d
- Synopsys · 57 open roles · median 61 d
- NVIDIA · 45 open roles · median 76 d
- Micron Technology · 39 open roles · median 104 d
- Qualcomm · 37 open roles · median 65 d
- Intel Corporation · 26 open roles · median 25 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.