Product Architectural Model Development Leader - San Jose, California, United States
$231,500 - $341,075 USD yearly
Originally posted 5 October 2026 by the employer.
About the role
The behavioral models become the single source of truth for architects, verification teams, RTL design teams, and software/compiler teams.
What you'll do
- Lead a team of behavioral modeling engineers developing cycle-approximate and functional models of FPGA architecture (fabric, DSP blocks, memory hierarchies, hard IP, transceivers, NoC).
- Define modeling methodology, coding standards, and architecture for behavioral models (C++, SystemC, Python).
- Partner with silicon architects to translate architectural specifications into executable behavioral models.
- Establish the architectural model as a trusted internal product reference for intended system behavior, functional flows, interfaces, and architectural rules.
- Collaborate with verification teams to ensure behavioral models serve as golden references/scoreboards for RTL verification (UVM environments, formal checking, co-simulation).
- Establish and maintain simulation infrastructure, regression frameworks, and CI pipelines for model validation.
What you'll need
- Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.
- 15+ years of experience in silicon architecture, design, or verification, with 5+ years in a technical leadership role.
- Strong hands-on experience developing behavioral, functional, or performance models in C++, SystemC, and/or System Verilog.
- Deep understanding of FPGA or ASIC architecture fundamentals (fabric architecture, memory subsystems, interconnect, hard IP blocks).
- Experience bridging architecture specifications into simulatable models used for verification and/or performance analysis.
- Familiarity with RTL design and verification flows (SystemVerilog/UVM) sufficient to reason about model-RTL equivalence.
Nice to have
- Prior experience specifically with FPGA architecture (embedded memory, transceivers, NoC/interconnect).
- Experience with performance/pathfinding modeling for PPA trade-off studies.
- Experience building or maintaining spec-to-model or model-to-RTL automation/codegen flows.
- Familiarity with formal methods or golden-model-based verification methodologies.
- Experience supporting early software/compiler enablement using pre-silicon models.
- Experience delivering customer-consumable pre-silicon models or integrating architectural models into FPGA/ASIC development tools for early customer prototyping.
Skills: behavioral models, architectural models, FPGA silicon, architecture definition, golden-reference checking
This role has been open 4 days — well below the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
461
|
Median days open
76 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (461 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 461 |
| Open roles in the wider Digital Design & Verification family | 23 | 3183 · 114 employers |
| Median days open | 16 d | 76 d (−60 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: behavioral models, architectural models, FPGA silicon, architecture definition, golden-reference checking
Who's hiring in this category
- Qualcomm · 77 open roles · median 79 d
- NVIDIA · 60 open roles · median 63 d
- AMD · 36 open roles · median 58 d
- Apple · 32 open roles · median 3 d
- Arm Holdings · 27 open roles · median 106 d
- NXP Semiconductors · 21 open roles · median 108 d
How we counted: 461 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.