Process Integration Program Engineer
Originally posted 6 August 2026 by the employer.
About the role
As an ID1 Process Integration Program Engineer, you will manage part type introductions, wafer resource planning, and yield performance throughout the product lifecycle. The role supports bringing DRAM and NAND products from concept to high-volume production.
What you'll do
- Manage system setup, traveler creation, and pilot scheduling for new product introductions.
- Coordinate startup planning activities, including risk assessments and resource alignment.
- Support yield curve projections and performance tracking to enable business planning and forecasting.
- Oversee sampling plans, attribute management, SWR processing, and hold management activities.
- Partner with planning, operations, and engineering teams to manage wafer, reticle, and priority lot requirements.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Chemical Engineering, Materials Science, Physics, or a related engineering field.
- Experience in semiconductor manufacturing, product introduction, PTO, NPI, or related engineering disciplines.
- Knowledge of DRAM and/or NAND technologies.
- Analytical, problem-solving, communication, and cross-functional collaboration skills.
Nice to have
- Experience in PTO (Part Type Ownership) or New Product Introduction within a DRAM or NAND manufacturing environment.
- Experience coordinating wafer planning, yield performance monitoring, and product lifecycle transitions.
- Familiarity with manufacturing systems, attribute management, and reticle tracking processes.
- Experience collaborating across engineering, planning, and operations organizations in a high-volume manufacturing environment.
- Experience using AI-assisted analytics to enhance data interpretation, anomaly detection, and yield improvement initiatives.
Skills: new product introductions, yield curve projections, wafer planning, attribute management, reticle tracking
More semiconductor jobs: Micron Technology jobs · Product engineer jobs
This role has been open 91 days — well above the 65-day median for Product Engineering roles.
Product Engineering · Memory Design
|
Open roles in category
83
|
Median days open
65 d
|
Category median salary (all employers)
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (83 roles · 10 employers) |
|---|---|---|
| Open roles in this specialty | 54 | 83 |
| Open roles in the wider Silicon Validation & Test family | 176 | 2382 · 120 employers |
| Median days open | 82 d | 65 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: new product introductions, yield curve projections, wafer planning, attribute management, reticle tracking
Who's hiring in this category
- Micron Technology (this employer) · 54 open roles · median 83 d
- SanDisk · 14 open roles · median 7 d
- KIOXIA America · 4 open roles · median 35 d
- Cadence Design Systems · 3 open roles · median 226 d
- OmniVision · 2 open roles · median 178 d
- Solidigm · 2 open roles · median 15 d
How we counted: 83 open Product Engineering (Memory Design) roles from 10 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.