Prinicipal Signal Integrity Engineer - CA, San Jose, United States
Originally posted 28 September 2026 by the employer.
About the role
This role involves analyzing, modeling, and validating the complex interconnects of high-speed Serializer/De-serializer (SerDes) channels @56/64/112/128/224+ Gbps, LPDDR4/5x/6, DDR5, PCIe Gen 5/6, and 400/800/1600Gbps Ethernet links.
What you'll do
- Model and simulate end-to-end high-speed channels including transceivers, IC package, PCB, and cross-boards connectors/cables.
- Utilize industry-standard tools and methodologies to perform time/frequency domain signal integrity analysis (IBIS-AMI, SPICE, full-wave EM analysis).
- Identify link quality issues such as loss, reflection, and crosstalk, and resolve them.
- Conduct channel-simulations to optimize Eye Diagram, Bit Error Rate (BER), and Signal-Noise-Ratio (SNR) for high-speed signaling.
- Interpret simulation results to provide design guidelines on board materials, stack-up, transmission line routings, component placement, and layout optimization.
- Review PCB layout and board material/stack-up, identify potential signal integrity and power integrity issues, and propose solutions.
- Support lab validation and debugging to correlate with simulation data.
What you'll need
- Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field.
- Strong experience in high-speed signal integrity engineering.
- Proficiency in SI simulation tools.
- Strong expertise in high-speed architecture, interconnects, and PCB/package design.
- Knowledge of high-speed interfaces (PCIe, Ethernet, DDR).
- Familiarity with MATLAB or Python for data analysis and automation.
- Hands-on experience with lab testing tools (TDR, VNA, high-speed oscilloscopes).
Nice to have
- Proficiency in SI simulation tools (Keysight ADS, Cadence Sigrity, Ansys HFSS).
Skills: SerDes, signal integrity, IBIS-AMI, PCIe, DDR
This role has been open 11 days — well below the 77-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
242
|
Median days open
77 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (242 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 242 |
| Open roles in the wider Analog & Mixed-Signal family | 40 | 1413 · 106 employers |
| Median days open | 38 d | 77 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes, signal integrity, IBIS-AMI, PCIe, DDR
Who's hiring in this category
- AMD (this employer) · 30 open roles · median 37 d
- Synopsys · 29 open roles · median 25 d
- Cadence Design Systems · 19 open roles · median 183 d
- Qualcomm · 19 open roles · median 58 d
- Micron Technology · 13 open roles · median 70 d
- Apple · 12 open roles · median 11 d
How we counted: 242 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.