Principal Verification Engineer - San Jose, California, United States
$185,000 - $230,000 USD yearly
Originally posted 29 September 2026 by the employer.
This role involves the functional verification of ASICs with CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
About the role
This role involves full lifecycle verification for complex ASICs, from planning and test development to debugging and coverage closure.
What you'll do
- Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
- Collaborate with software and system validation teams to create and execute test plans on emulation platforms.
- Apply both directed and constrained-random verification techniques using SystemVerilog/UVM.
- Debug test failures, analyze coverage results, and close functional coverage gaps.
- Work with RTL designers to troubleshoot and resolve design issues.
- Drive verification strategy and methodology for SoCs in server and networking applications.
What you'll need
- Bachelor’s degree in Electrical Engineering.
- 8+ years of experience in SoC verification for server and networking applications.
- Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
- Proficiency with industry-standard simulators, version control, and regression systems.
- Strong debugging and coverage analysis skills.
- Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
- Familiarity with verification of switching architectures, including packet processing and forwarding engines.
Nice to have
- Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
- Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
- Knowledge of Ethernet/PCIe switching and central buffer architectures.
- Experience with emulation platforms and hardware-software co-verification.
Skills: SystemVerilog, UVM, functional verification, coverage closure, ASICs
This role has been open 0 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1169
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1169 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 1169 |
| Open roles in the wider Digital Design & Verification family | 58 | 3109 · 115 employers |
| Median days open | 33 d | 63 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SystemVerilog, UVM, functional verification, coverage closure, ASICs
Who's hiring in this category
- AMD · 104 open roles · median 39 d
- Qualcomm · 97 open roles · median 53 d
- NVIDIA · 86 open roles · median 70 d
- Synopsys · 62 open roles · median 23 d
- SiFive · 57 open roles · median 56 d
- NXP Semiconductors · 52 open roles · median 76 d
How we counted: 1169 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.