Principal Verification Engineer - Austin (Oakhill, Office), United States
Originally posted 10 June 2026 by the employer. Relisted by the employer on 27 August 2026.
Verify digital IPs within the MME MCU/MPU Digital IP team using UVM, SVA, and formal verification methodologies.
About the role
This position is within the MME MCU/MPU Digital IP team verifying digital IPs for automotive and microcontroller applications.
What you'll do
- Define and execute verification plans while mentoring a team of engineers. - Develop and implement verification testbenches, including drivers, monitors, scoreboards, and UVM VIPs. - Develop directed and constrained-random stimulus, alongside SystemVerilog assertions (SVA). - Analyze RTL, functional coverage, and assertion coverage results, and define functional coverage models. - Apply formal verification methodologies to resolve verification challenges. - Perform failure reproduction, root-cause analysis, and test pattern debugging across simulation environments.
What you'll need
- BSEE with 5+ years of semiconductor industry experience, MSEE with 3+ years, or PhD with 1+ years. - Strong expertise in Verilog and SystemVerilog. - Experience with OVM/UVM and class-based verification methodologies. - Experience with formal verification methodologies. - Knowledge of protocols such as DDR, PCIe, and AMBA (CHI, ACE, AXI). - Scripting proficiency in Python, Perl, and UNIX/Linux.
Nice to have
- Familiarity with major simulation and debug tools. - VHDL knowledge. - Experience leveraging AI/LLM-based approaches to improve engineering efficiency.
Skills: UVM, SystemVerilog, formal verification, functional coverage, assertions
This role has been open 122 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 1241 |
| Open roles in the wider Digital Design & Verification family | 131 | 3298 · 115 employers |
| Median days open | 94 d | 65 d (+29 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, formal verification, functional coverage, assertions
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.