Principal TPIP/HSIO Engineer
$262,700 - $355,400 USD yearly
Lead pre-silicon quality, vendor harmonization, and silicon-to-simulation correlation for DDR, PCIe, and SerDes HSIO subsystems.
Originally posted 29 October 2026 by the employer.
About the role
As a Principal TPIP Quality Engineer, you will lead pre-silicon quality for high-speed I/O (HSIO) subsystems across DDR, PCIe, and eUSB blocks. You will partner with third-party IP vendors, integration teams, and architects to achieve DFX targets from simulation through post-silicon characterization.
What you'll do
- Collaborate with IP vendors and internal integration, architecture, DV, DFT, and PTE teams on HSIO blocks including DDR, PCIe, eUSB, and D2D.
- Drive closure on DFX metrics, including test coverage, margin analysis, stuck-at/scan coverage, and clock-domain checks.
- Develop and maintain methodologies to correlate post-silicon measurements (eye-diagrams, BER, BIST logs) back to design and simulation data.
- Chair the DDR and PCIe TPIP Councils to harmonize quality criteria, test architectures, and vendor deliverables across projects.
- Partner with Architecture, Integration, Validation, Package, and SIPI teams to address integration challenges.
What you'll need
- Bachelor’s or Master’s in Electrical Engineering or a related field.
- 10+ years of experience in high-speed interface design, validation, or bring-up (DDR, PCIe, SerDes).
- Proven track record in post-silicon characterization (BER, margining) and correlating measurements with pre-silicon simulations.
- Strong scripting skills in Python and TCL for data parsing, test automation, and result visualization.
- Experience driving technical discussions across external vendors and internal cross-functional teams.
Skills: HSIO, DDR, PCIe, SerDes, post-silicon characterization, BER
More semiconductor jobs: Arm Holdings jobs · Signal integrity jobs
This role has been open 4 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
250
|
Median days open
76 d
|
Category median salary (all employers)
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (250 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 250 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1484 · 106 employers |
| Median days open | 5 d | 76 d (−71 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: HSIO, DDR, PCIe, SerDes, post-silicon characterization, BER
Who's hiring in this category
- Synopsys · 34 open roles · median 37 d
- AMD · 26 open roles · median 49 d
- Cadence Design Systems · 21 open roles · median 147 d
- Qualcomm · 17 open roles · median 81 d
- NVIDIA · 16 open roles · median 208 d
- Micron Technology · 12 open roles · median 47 d
How we counted: 250 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.