Principal Test Engineer, Test Architecture - San Jose, United States
Originally posted 17 September 2026 by the employer.
About the role
This role defines and drives test architecture, methodology, and innovation for analog and mixed-signal semiconductor products. It focuses on semiconductor test methodology, design-for-test strategy, test infrastructure, and process optimization across analog and mixed-signal product portfolios.
What you'll do
- Define and drive test architecture, methodology, and innovation for analog and mixed-signal semiconductor products.
- Partner with IC design, product engineering, and test engineering teams to establish design-for-test (DFT) requirements and optimize product testability.
- Architect and optimize mixed-signal test hardware and software solutions to improve test quality, throughput, cost, and manufacturability.
- Evaluate and influence tester roadmap, test methodologies, and process improvements.
- Provide technical leadership and mentorship on test strategies, best practices, and problem-solving for complex semiconductor products.
What you'll need
- BS or MS in Electrical Engineering, Physics, or a related technical discipline with 10+ years of experience in semiconductor test engineering or a closely related field.
- Extensive Automatic Test Equipment (ATE) development experience and proven track record developing production test solutions on platforms such as Advantest 93K, ETS, Teradyne FLEX, Diamondx, LTX, SPEA, or similar systems.
- Experience designing test hardware and software for mixed-signal test solutions, including wafer sort and final test.
- Experience with all aspects of new product introduction, from customer samples and qualification to characterization and production test systems.
- Experience testing analog, mixed-signal, data converter, power management, and related semiconductor devices.
- Familiarity with digital interfaces, memory technologies, and their theory of operation.
- Thorough understanding of electrical engineering principles.
Nice to have
- Experience with analog or mixed-signal IC design and related development tools.
This role has been open 25 days — below the 27-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
526
|
Median days open
27 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (526 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 42 | 526 |
| Open roles in the wider Silicon Validation & Test family | 114 | 2199 · 111 employers |
| Median days open | 23 d | 27 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Who's hiring in this category
- Teradyne · 67 open roles · median 25 d
- Renesas Electronics (this employer) · 41 open roles · median 25 d
- Infineon Technologies · 39 open roles · median 35 d
- Micron Technology · 28 open roles · median 34 d
- AMD · 26 open roles · median 40 d
- Qualcomm · 25 open roles · median 27 d
How we counted: 526 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.