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Marvell Technology

Principal Test Development Engineer - Santa Clara, CA, United States

Marvell Technology Santa Clara, CA, United States 1 day ago
Verification, Validation & Test

Originally posted 24 October 2026 by the employer.

Advantest 93K test program development and tester hardware design for high-speed silicon testing.

About the role

As a Principal Test Development Engineer in the Operations business group, you will test features on silicon semiconductor chips produced for internal and external customers to ensure shipped units meet specifications.

What you'll do

- Develop test programs on the Advantest 93K tester platform and design tester hardware for high-speed testing. - Develop characterization, production, and wafer sort test programs on the Advantest 93K tester. - Create documentation for detailed test plans and test methodologies to meet product specifications. - Participate in testability reviews with DFT/DFM teams to define and enhance yield and test methodologies. - Convert test patterns from the design simulation environment to ATE format. - Drive test flow optimization, test time reduction, insertion removals, yield improvement, and production test program releases.

What you'll need

- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5-10 years of experience, or a Master's degree with 3-5 years of experience. - Minimum 6+ years of test program development experience on the Advantest 93K ATE tester platform. - Demonstrable experience in ATE testing, test methodology, silicon process, and DFT/DFM. - 4+ years of high-speed digital testing experience. - Demonstrable experience with C/C++, Perl, Python, and the Linux environment.

Market context

This role has been open 0 days — well below the 36-day median for Silicon Test Engineering roles.

Silicon Test Engineering · DFT Test

Open roles in category
564
Median days open
36 d
Median salary
$176k
See the full market breakdown ▾Category comparison, and who else is hiring
How Marvell Technology compares in Silicon Test Engineering hiring
Metric Marvell Technology All employers we track in this specialty (564 roles · 78 employers)
Open roles in this specialty 19 564
Open roles in the wider Silicon Validation & Test family 60 2238 · 112 employers
Median days open 32 d 36 d (−4 d vs this employer)
Median salary (USD postings) — $176k

Who's hiring in this category

  • Teradyne · 75 open roles · median 28 d
  • Infineon Technologies · 46 open roles · median 40 d
  • Renesas Electronics · 44 open roles · median 30 d
  • Qualcomm · 31 open roles · median 36 d
  • Texas Instruments · 29 open roles · median 31 d
  • Micron Technology · 28 open roles · median 40 d

How we counted: 564 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.

Apply now
Santa Clara, CA, United States
On-site
1 day ago

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