Principal System Diagnostics Engineer - Santa Clara, CA, United States
$150,680 - $225,700 USD yearly
Originally posted 15 October 2026 by the employer.
This team performs analog validations on amplifiers that drive optical electronic devices and receivers.
About the role
This role involves helping to deliver high bandwidth over long distances by performing analog validations on amplifiers that drive optical electronic devices and receivers.
What you'll do
- Design and implement low-level diagnostic software, test suites, and APIs to validate network switch hardware components.
- Develop test plans to verify ASICs, high-speed SerDes, memory interfaces (DDR/HBM), PCIe buses, power management, and thermal control systems.
- Partner with hardware design and silicon teams during initial board bring-up, debugging early prototype hardware, and isolating root-cause issues.
- Deliver diagnostic test coverage for integration into factory manufacturing lines to ensure high-quality production standards.
- Build automated testing frameworks and scripts to execute diagnostic software, collect metrics, and analyze failure data.
- Work with Hardware Engineering, ASIC Design, Embedded Firmware, and Network OS teams to define diagnostic requirements and hardware-testability (DFT) hooks.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 10-15 years of related professional experience; Master's degree with 5-10 years of experience.
- Proficient in C/C++ for embedded or low-level software development, along with scripting skills in Python or Bash.
- Solid understanding of switch architecture, high-speed signal integrity, SerDes, I2C/SPI/MDIO protocols, PCIe, and peripheral management.
- Experience developing in Linux environments, including Linux drivers, kernel concepts, and memory mapping.
- Hands-on experience using lab equipment such as oscilloscopes, logic analyzers, and JTAG debuggers to isolate hardware vs. software bugs.
Nice to have
- Experience with networking ASICs or switch silicon from vendors like Broadcom, Marvell, or Intel (Barefoot).
- Familiarity with networking protocols (Ethernet, TCP/IP, Layer 2/3 switching) and optical transceivers.
- Knowledge of U-Boot, Open Network Install Environment (ONIE).
- Exposure to rack-scale management: BMC (OpenBMC), PDU, IPMI, or Redfish.
- Experience with continuous integration (CI/CD) pipelines and automated test infrastructure.
- Proven experience managing test relationships with ODM/JDM or CM partners.
Skills: low-level diagnostic software, test suites, board bring-up, debugging, lab equipment, hardware-testability (DFT) hooks
This role has been open 0 days — well below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
412
|
Median days open
41 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (412 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 412 |
| Open roles in the wider Silicon Validation & Test family | 55 | 2216 · 112 employers |
| Median days open | 20 d | 41 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: low-level diagnostic software, test suites, board bring-up, debugging, lab equipment, hardware-testability (DFT) hooks
Who's hiring in this category
- AMD · 58 open roles · median 41 d
- Micron Technology · 39 open roles · median 37 d
- Qualcomm · 37 open roles · median 27 d
- NVIDIA · 25 open roles · median 22 d
- Graphcore · 21 open roles · median 120 d
- Microchip Technology · 20 open roles · median 70 d
How we counted: 412 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.