Principal/ Sr.Principal Digital Design Engineer - San Jose, California, United States
$185,000 - $230,000 CAD yearly
Originally posted 14 September 2026 by the employer.
About the role
This role involves architecting and implementing digital designs for high-performance AI connectivity solutions, owning complex blocks from micro-architecture through silicon bring-up. The position focuses on delivering production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.
What you'll do
- Develop and implement complex digital blocks and subsystems, defining micro-architecture and driving RTL implementation.
- Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features.
- Drive designs to production, ensuring quality, schedule, and overall design success.
- Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
- Own third-party IP integration and block-level verification through sign-off.
- Work closely with post-silicon teams to facilitate silicon bring-up and debug.
What you'll need
- Bachelor's degree in Electrical Engineering or equivalent.
- 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
- Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis.
- Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation.
- Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar.
- Production experience with advanced CMOS nodes (≤7nm).
- Proficiency with Cadence and/or Synopsys digital design flows.
Nice to have
- Master's degree in Electrical Engineering or related field.
- Track record of delivering multiple high-performance designs to production in data-center environments.
- Hands-on collaboration with embedded firmware teams; understanding of firmware development challenges.
- Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.).
- Proven contributions to design methodology, CAD automation, or design infrastructure.
This role has been open 24 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1010
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1010 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 1010 |
| Open roles in the wider Digital Design & Verification family | 62 | 3195 · 113 employers |
| Median days open | 29 d | 62 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 143 open roles · median 60 d
- Synopsys · 82 open roles · median 24 d
- AMD · 73 open roles · median 35 d
- Analog Devices · 48 open roles · median 40 d
- NXP Semiconductors · 48 open roles · median 77 d
- NVIDIA · 45 open roles · median 63 d
How we counted: 1010 open Digital/RTL Design (RTL Design) roles from 97 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.