Principal SoC Performance Architect – Next-Generation Server Platforms - San Jose, California, United States
$262,700 - $355,400 USD yearly
Originally posted 9 June 2026 by the employer.
About the role
This role operates at the intersection of architecture, workload characterization, and silicon-level analysis to evaluate and optimize server platforms.
What you'll do
- Evaluate and analyze real-world workloads on production silicon, focusing on AI at scale and HPC applications. - Partner with multi-functional teams to define performance metrics, representative use cases, and benchmarking strategies. - Design and implement targeted microbenchmarks to isolate and study specific architectural behaviors. - Identify performance bottlenecks through detailed analysis and recommend actionable optimizations. - Translate insights from workload and silicon studies into architectural improvements for performance and scalability. - Collaborate with hardware and software teams to influence system-level design decisions and guide technical teams.
What you'll need
- Master's or PhD degree in Computer Engineering, Computer Science, or a related field. - 10+ years of experience in system or hardware architecture, with exposure to CPU/accelerator architectures, cache and memory subsystems, or PCIe, networking, or storage. - Background in high-performance IO/networking (such as PCIe, CXL, InfiniBand, RoCE) or performance optimization for HPC or cloud-scale systems. - Proven expertise in benchmarking methodologies and development of custom microbenchmarks. - Experience with performance analysis tools, profiling, and simulation environments. - Proficiency in SystemC, TLM, C++, and Python, with the ability to navigate large codebases.
Nice to have
- Experience working directly with silicon bring-up or post-silicon performance analysis. - Familiarity with performance simulators or architectural modeling tools.
Skills: workload analysis, performance bottlenecks, architectural improvements, CPU/accelerator architectures, cache and memory subsystems, PCIe, networking
This role has been open 120 days — well above the 76-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
479
|
Median days open
76 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (479 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 479 |
| Open roles in the wider Digital Design & Verification family | 104 | 3298 · 115 employers |
| Median days open | 120 d | 76 d (+44 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: workload analysis, performance bottlenecks, architectural improvements, CPU/accelerator architectures, cache and memory subsystems, PCIe, networking
Who's hiring in this category
- Qualcomm · 79 open roles · median 85 d
- NVIDIA · 54 open roles · median 71 d
- Apple · 38 open roles · median 14 d
- AMD · 35 open roles · median 71 d
- Arm Holdings (this employer) · 27 open roles · median 119 d
- Micron Technology · 22 open roles · median 111 d
How we counted: 479 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.