Principal SoC Design Engineer / SoC Lead - Austin, Texas, United States
Originally posted 3 September 2026 by the employer.
Own the integration of a full chip or major module/subsystem for a system built around a bandwidth problem in silicon photonics.
About the role
You will be the SoC Lead who owns the integration of the full chip, or a major module or subsystem, for a system built around a bandwidth problem. This role involves making and defending decisions across DFT, power, timing, and interconnect architecture, with an understanding of tapeout implications.
What you'll do
- Lead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows.
- Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
- Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
- Go deep on any domain when needed, staying hands-on with the flow at every level.
- Help scale the design organization: hire, mentor, and grow engineers across specialty domains.
- Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs.
What you'll need
- Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.
- Demonstrated breadth across domains, such as closing timing on a block and arguing interconnect architecture in the same design cycle.
- Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design.
- Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.
Nice to have
- Cadence toolchain experience.
- Familiarity with AI/ML accelerator or large-scale compute workloads.
- Familiarity with AI-assisted EDA flows in the Cadence toolchain (e.g., Cerebrus) for synthesis, timing closure, or verification.
Skills: SoC integration, DFT, power, timing, interconnect architecture, multiple full-chip tapeouts
This role has been open 41 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Neurophos | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 470 |
| Open roles in the wider Digital Design & Verification family | 3 | 3188 · 115 employers |
| Median days open | 41 d | 79 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: SoC integration, DFT, power, timing, interconnect architecture, multiple full-chip tapeouts
Who's hiring in this category
- Qualcomm · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.