Principal Silicon Photonics Wafer Test Engineer - Fremont, CA, United States
Originally posted 9 September 2026 by the employer.
Develop wafer-level test and characterization methodologies for photonic integrated circuits (PICs) and associated test structures.
About the role
This role involves providing technical leadership in the development, implementation, and continuous improvement of silicon photonics wafer-level test and characterization methodologies for photonic integrated circuits (PICs) and associated test structures. A key focus is on developing robust wafer-test methodologies and platforms that integrate electrical and RF probing, optical alignment and coupling, instrumentation, automation software, and wafer-level data analysis.
What you'll do
- Provide technical leadership for the development, implementation, and continuous improvement of silicon photonics wafer-level test and characterization methodologies.
- Develop and optimize wafer-level characterization methods for active and passive silicon photonic devices, including modulators, photodetectors, waveguides, couplers, resonators, and integrated photonic circuits.
- Lead RF and high-speed electro-optical wafer characterization, including S-parameter measurements, frequency response, bandwidth, impedance characterization, calibration, de-embedding, and signal-integrity analysis.
- Develop and maintain test automation and data-analysis software using Python, including instrument control, wafer navigation, optical alignment, test sequencing, error handling, and automated data processing.
- Analyze wafer-level characterization data and wafer maps to identify device distributions, spatial trends, process variation, systematic effects, yield limiters, and test-related artifacts.
- Partner with device design, process integration, and foundry teams to correlate wafer-test results with device physics, fabrication processes, process-control monitors, and design parameters.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering, Optical Engineering, Physics, or a related field.
- Minimum of 5 years of hands-on laboratory experience in photonics, semiconductor, or optoelectronic device testing.
- Experience with commercial wafer-testing stations and electrical/RF probing of semiconductor devices.
- Experience with optical alignment with lenses or fibers to semiconductor devices.
- Strong understanding of silicon photonic devices, including modulators, photodetectors, passive optical structures, and optical coupling techniques.
- Experience developing automated laboratory or production test systems using Python or comparable programming languages.
- Strong hands-on experience with RF/microwave measurement techniques, including vector network analyzers, S-parameters, RF probing, calibration, and de-embedding.
- Experience with data plotting and analysis software such as JMP, MATLAB, or python.
This role has been open 35 days — slightly above the 28-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
542
|
Median days open
28 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Coherent Corp | All employers we track in this specialty (542 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 542 |
| Open roles in the wider Silicon Validation & Test family | 11 | 2224 · 112 employers |
| Median days open | 35 d | 28 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Who's hiring in this category
- Teradyne · 72 open roles · median 27 d
- Renesas Electronics · 45 open roles · median 22 d
- Infineon Technologies · 41 open roles · median 37 d
- Micron Technology · 27 open roles · median 35 d
- Qualcomm · 27 open roles · median 27 d
- AMD · 25 open roles · median 42 d
How we counted: 542 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.