Principal Signal Integrity Engineer (SI/PI) - CA, San Jose, United States
Originally posted 24 September 2026 by the employer.
This role drives SI/PI strategy and execution for FPGA and adaptive computing products.
About the role
This role leads Signal and Power Integrity development as a Principal Engineer within AMD's Adaptive and Embedded Computing Group (AECG), driving SI/PI strategy and execution across silicon, package, board, and system-level designs.
What you'll do
- Develop technical solutions for Signal Integrity and Power Integrity.
- Drive system-level SI/PI architecture, design guidelines, and layout recommendations.
- Perform end-to-end channel simulations for high-speed serial interfaces and memory subsystems.
- Lead SI/PI analysis and optimization of DDR4, DDR5, LPDDR4, LPDDR5, HBM, and other high-performance memory interfaces.
- Correlate simulations with lab measurements and drive root-cause analysis of signal and power integrity issues.
- Collaborate with silicon, package, PCB, architecture, and manufacturing teams to resolve complex SI/PI challenges.
What you'll need
- Deep Signal Integrity expertise and a solid understanding of Power Integrity fundamentals.
- Advanced simulation expertise with hands-on lab measurement and debug experience.
- Experience with DDR, LPDDR, HBM, or other high-performance memory interfaces.
- Experience with FPGA, adaptive computing, ASIC, networking, datacenter, or high-performance computing platforms.
- Expertise with SI/PI analysis tools including ADS and HFSS.
- Strong foundation in electromagnetic theory, transmission lines, and circuit analysis.
Nice to have
- Hands-on experience performing lab measurements and correlating hardware results to simulation models.
- Experience with PCB, package, and IC-level power delivery networks.
- Experience with SIwave and HSPICE.
- Experience with programming in Python, C++, Matlab.
- MS or PhD in Electrical Engineering.
Skills: Signal and Power Integrity, high-speed serial interfaces, DDR4, DDR5, LPDDR4, LPDDR5, HBM, channel simulations, lab measurements
This role has been open 15 days — well below the 77-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
242
|
Median days open
77 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (242 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 30 | 242 |
| Open roles in the wider Analog & Mixed-Signal family | 40 | 1413 · 106 employers |
| Median days open | 38 d | 77 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: Signal and Power Integrity, high-speed serial interfaces, DDR4, DDR5, LPDDR4, LPDDR5, HBM, channel simulations, lab measurements
Who's hiring in this category
- AMD (this employer) · 30 open roles · median 37 d
- Synopsys · 29 open roles · median 25 d
- Cadence Design Systems · 19 open roles · median 183 d
- Qualcomm · 19 open roles · median 58 d
- Micron Technology · 13 open roles · median 70 d
- Apple · 12 open roles · median 11 d
How we counted: 242 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.