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Synopsys

Principal SerDes Systems Engineer

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Eindhoven, Netherlands 8 months ago
Analog & Mixed-Signal Design

Originally posted 2 March 2026 by the employer.

This role focuses on SerDes system models for NRZ and PAM4 transceivers.

About the role

This role involves developing and maintaining SerDes system models and advanced algorithms for high-speed serial-link transceiver development, targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.

What you'll do

  • Develop and maintain SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
  • Run comprehensive system simulations to verify design performance across multiple protocols and channels.
  • Design and propose advanced algorithms to calibrate and adapt transceivers for optimal performance.
  • Correlate simulated performance with silicon measurements.
  • Provide expert assistance to customers for system-level performance issues and troubleshooting.
  • Contribute to lab testing and analysis for high-speed serial links.

What you'll need

  • M.Sc. or Ph.D. in Electrical or Computer Engineering.
  • Strong experience modeling circuits and systems in MATLAB/Simulink.
  • Expertise in designing high-speed analog CMOS circuits.
  • Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
  • Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
  • Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
  • Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
  • Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/SystemVerilog.

Skills: SerDes system models, PAM4 transceivers, PCIe, Ethernet, DSP, high-speed serial links

Market context

This role has been open 166 days — well above the 71-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category
247
Median days open
71 d
Median salary
$191k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in High-Speed IO/SerDes Design hiring
Metric Synopsys All employers we track in this specialty (247 roles · 47 employers)
Open roles in this specialty 34 247
Open roles in the wider Analog & Mixed-Signal family 51 1461 · 106 employers
Median days open 36 d 71 d (−35 d vs this employer)
Median salary (USD postings) — $191k

Skills observed across this category: SerDes system models, PAM4 transceivers, PCIe, Ethernet, DSP, high-speed serial links

Who's hiring in this category

  • Synopsys (this employer) · 34 open roles · median 36 d
  • AMD · 27 open roles · median 45 d
  • Cadence Design Systems · 21 open roles · median 140 d
  • Qualcomm · 21 open roles · median 69 d
  • Micron Technology · 13 open roles · median 41 d
  • Apple · 12 open roles · median 25 d

How we counted: 247 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Eindhoven, Netherlands
On-site
8 months ago

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