Principal SerDes Bring-up Validation Engineer - San Jose, California, United States
$185,000 - $240,000 USD yearly
Originally posted 31 July 2026 by the employer. Relisted by the employer on 5 October 2026.
This role focuses on SerDes bring-up and validation within Astera Labs' CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies.
About the role
As a Principal SerDes Bring-up Validation Engineer, you will join a mixed-signal design team to lead end-to-end post-silicon bring-up, validation, and characterization. This involves owning bring-up and characterization strategies from conception and driving hands-on lab work to verify silicon against specification and performance targets.
What you'll do
- Design, develop, and execute bring-up plans, translating design and product requirements into measurable test objectives and schedules.
- Drive design reviews and specification alignment to ensure testability and influence design tradeoffs for performance and reliability.
- Lead hands-on test execution and bring-up, performing silicon block level bring-up, functional, parametric, and interoperability testing.
- Build and maintain automation frameworks, developing scalable test automation, data capture, and analysis pipelines.
- Debug and optimize system performance, diagnosing complex failures across analog, digital, firmware, and protocol layers.
- Develop robust Python test scripts and control interfaces to configure, monitor, and collect status from multiple DSP and hardware platforms.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8-12 years of hands-on experience in mixed-signal, high-speed lab environments executing characterization and validation.
- Experience with protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.
- Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers.
- Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization).
- Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset and link sequencing.
- Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
Nice to have
- MS or PhD in Electrical Engineering or a related field to demonstrate advanced technical depth and specialization.
This role has been open 78 days — well above the 43-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
410
|
Median days open
43 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (410 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 410 |
| Open roles in the wider Silicon Validation & Test family | 20 | 2219 · 113 employers |
| Median days open | 104 d | 43 d (+61 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Who's hiring in this category
- AMD · 58 open roles · median 44 d
- Micron Technology · 39 open roles · median 40 d
- Qualcomm · 36 open roles · median 29 d
- NVIDIA · 26 open roles · median 24 d
- Microchip Technology · 22 open roles · median 69 d
- Graphcore · 20 open roles · median 122 d
How we counted: 410 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.