Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet - San Jose, California, United States
$185,000 - $230,000 USD yearly
Originally posted 14 September 2026 by the employer.
About the role
This role involves leading design verification for connectivity IPs and SoCs.
What you'll do
- Lead verification strategy for complex IPs and SoC subsystems from architecture through silicon.
- Define verification methodologies, reusable verification frameworks, and best practices.
- Drive verification planning, execution, coverage closure, and sign-off.
- Architect and develop scalable UVM/System Verilog verification environments.
- Develop constrained-random, coverage-driven verification methodologies.
- Debug complex RTL, protocol, timing, and integration issues.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Minimum 10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.
- Strong expertise in System Verilog and UVM.
- Extensive experience in verification planning, execution, and sign-off.
- Deep understanding of constrained-random verification and coverage-driven methodologies.
- Strong experience with assertions (SVA), functional coverage, and protocol compliance.
- Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.
- Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Nice to have
- CXL Cache, Memory, and I/O protocols
- PCIe Transaction, Data Link, and Physical Layers
- Ethernet MAC/PCS/PMA architecture
- Coherency protocols
- High-speed interconnects
- AI accelerator connectivity
- Data center SoC architecture
- Multi-chip and chiplet-based systems
- Performance verification
- Low-power verification
- CDC/RDC verification
- Formal Verification
- Portable Stimulus (PSS)
- Python, Perl, Tcl, or similar scripting languages
- Emulation and FPGA prototyping
- Experience leading verification for large SoCs or complex connectivity IPs.
- Proven success delivering multiple first-pass silicon programs.
- Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.
- Familiarity with customer-facing debug and post-silicon issue resolution.
- Contributions to verification methodology, reusable frameworks, or industry standards.
Skills: UVM/System Verilog, constrained-random verification, CXL, PCIe, Ethernet
This role has been open 24 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 1206 |
| Open roles in the wider Digital Design & Verification family | 62 | 3195 · 113 employers |
| Median days open | 54 d | 63 d (−9 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM/System Verilog, constrained-random verification, CXL, PCIe, Ethernet
Who's hiring in this category
- Qualcomm · 111 open roles · median 42 d
- AMD · 102 open roles · median 49 d
- NVIDIA · 76 open roles · median 62 d
- Synopsys · 61 open roles · median 25 d
- SiFive · 55 open roles · median 66 d
- Micron Technology · 52 open roles · median 98 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.