Originally posted 10 November 2026 by the employer.
About the role
This role drives packaging architecture decisions and customer integration for FPGA, embedded SoC, and custom ASIC programs within the AECG Packaging team. The scope covers IC-PKG-PCB co-design spanning 2.5D/3D, OPC, and MOP technologies from initial architecture through qualification.
What you'll do
- Drive packaging architecture decisions and IC-PKG-PCB co-design for FPGA, embedded SoC, and custom ASIC programs spanning 2.5D/3D, OPC, and MOP technologies.
- Lead DFM and DFMEA reviews and packaging supply qualification, partnering with OSAT and substrate suppliers on manufacturable, reliable solutions.
- Serve as the primary customer-facing contact for assigned programs, translating customer requirements into internal technical direction.
- Organize and lead cross-functional task forces across silicon design, packaging, SI/PI, thermal-mechanical, quality and reliability test, and supply chain.
- Resolve technical issues, align decisions across functional teams, and track commitments to genuine closure to keep programs on schedule.
What you'll need
- Bachelor's or Master's degree in Electrical, Materials, Mechanical, or Semiconductor Engineering, or a related field.
- Expert-level experience in semiconductor packaging technology integration, with working knowledge of 2.5D/3D integration, OPC, MOP, and IC-PKG-PCB co-design and co-development.
- Strong experience with DFM/DFMEA/PFMEA and packaging supply qualification across OSAT, substrate, and materials partners.
- Demonstrated experience engaging customers directly and coordinating cross-functional task forces to closure.
Nice to have
- Strong knowledge of SoC architecture and critical IP blocks (SerDes, PHYs, memory controllers, I/O subsystems) and how they drive packaging and interconnect requirements.
- Familiarity with IC-package-PCB co-design and analysis tools (e.g., Cadence, Synopsys, Ansys, or equivalent EDA platforms).
- Familiarity with UCIe (Universal Chiplet Interconnect Express) and other die-to-die/chiplet interconnect standards.
- Experience with signal integrity and power integrity (SI/PI) analysis across the package and board interconnect.
- Understanding of high-speed I/O interface design considerations at the package level and familiarity with DDR/memory interface routing, timing, and packaging constraints.
- Experience with power plane and PDN (power delivery network) optimization across silicon, package, and board.
Skills: 2.5D/3D, UCIe, IC-PKG-PCB co-design, SI/PI, DFM/DFMEA
More semiconductor jobs: AMD jobs · Advanced packaging jobs · California jobs
This role has been open 0 days — well below the 95-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
43
|
Median days open
95 d
|
Category median salary (all employers)
$215k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (43 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 43 |
| Median days open | 53 d | 95 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $215k |
Skills observed across this category: 2.5D/3D, UCIe, IC-PKG-PCB co-design, SI/PI, DFM/DFMEA
Who's hiring in this category
- Marvell Technology · 7 open roles · median 48 d
- Micron Technology · 5 open roles · median 160 d
- Intel Corporation · 4 open roles · median 54 d
- NVIDIA · 4 open roles · median 89 d
- Qualcomm · 4 open roles · median 125 d
- AMD (this employer) · 3 open roles · median 95 d
How we counted: 43 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.