Principal RTL Design Engineer, IO & Memory Systems - Austin, Texas, United States
Originally posted 14 September 2026 by the employer.
This role involves designing and implementing IO and memory subsystems within the DataScale® platform.
About the role
This role involves owning the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale® platform, which is central to delivering reliable, high-performance AI systems at scale.
What you'll do
- Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction.
- Drive feasibility studies and design trade-off analysis to meet PPA constraints.
- Own microarchitecture definition and specification for IO and memory subsystems.
- Deliver synthesizable SystemVerilog RTL for assigned blocks against functionality, performance, and power targets.
- Run the front-end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness.
- Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes.
What you'll need
- MS in Electrical Engineering, Computer Science, or a related field.
- 7+ years of experience in ASIC design.
- Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification.
- Experience with power, performance, or area optimization.
- Experience with two or more on-chip or chip-to-chip protocols and interfaces such as AXI, APB, PCIe, Ethernet, or UCIe.
- Experience with memory subsystems such as HBM and CXL.
Nice to have
- Experience taking one or more ASIC products from concept to silicon.
- Familiarity with emerging scale-up protocols (ESUN, SUE, UAL) and scale-out protocols such as Ultra Ethernet.
- Experience designing on-chip interconnect and traffic-management logic, including NoC fabrics, switches, arbiters, and quality-of-service or congestion control mechanisms.
- Knowledge of machine learning and hardware accelerator architectures.
This role has been open 20 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 968 |
| Open roles in the wider Digital Design & Verification family | 8 | 3109 · 114 employers |
| Median days open | 45 d | 62 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.