Principal RTL Design Engineer - Austin, Texas, United States
$180,000 USD yearly
Originally posted 19 August 2026 by the employer.
Design the RDU, a chip built on a dataflow architecture, for SambaNova’s AI accelerator.
About the role
As Principal RTL Design Engineer, you will own the microarchitecture and RTL for SambaNova's Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This senior individual contributor role involves taking a block from microarchitecture specification through RTL, quality closure, and tape-out, focusing on power, performance, and area trade-offs.
What you'll do
- Own microarchitecture and RTL for a major RDU block or subsystem, from specification through tape-out.
- Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle.
- Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring.
- Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions.
- Partner with design verification to define verification intent and coverage and support debug of functional and gate-level failures.
- Work with architects and software teams to prototype and evaluate features that improve application-level performance.
What you'll need
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
- 7+ years of industry experience in ASIC RTL design.
- Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA.
- High-frequency design experience, including datapath pipelining, retiming, and critical-path restructuring.
- Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures.
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC.
- Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team.
- Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows.
- Scripting in Python for design and flow automation.
Nice to have
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
- Depth in compute and dataflow datapath, on-chip network and interconnect, or memory subsystem.
- Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, HBM, or DDR.
- AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures.
- Formal property checking applied to design intent.
- Advanced TSMC nodes and multi-die or chiplet design.
- Performance modeling and analysis to support architectural trade-offs.
- Fluency with Claude or other AI tools applied to RTL design and flow development.
This role has been open 58 days — below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1021 |
| Open roles in the wider Digital Design & Verification family | 7 | 3198 · 115 employers |
| Median days open | 58 d | 62 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 62 d
- Synopsys · 85 open roles · median 30 d
- AMD · 71 open roles · median 36 d
- Analog Devices · 48 open roles · median 50 d
- NVIDIA · 46 open roles · median 64 d
- NXP Semiconductors · 41 open roles · median 85 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.