Principal Product Applications Engineer – Memory & CXL - San Jose, California, United States
$175,000 - $230,000 USD yearly
Originally posted 29 April 2026 by the employer.
Support the customer deployment and debug of Leo Smart Memory Controller and Extender solutions across server and AI platforms.
About the role
Astera Labs is looking for a Principal Product Applications Engineer to support the deployment of Leo Smart Memory Controller and Extender solutions in server, AI, and datacenter platforms. This role focuses on memory architecture, system integration, hardware and software debug, and customer engineering.
What you'll do
- Serve as a technical point of contact for customers integrating Leo products into server, AI, and datacenter platforms. - Support customer platform bring-up, integration, debug, and production deployment. - Troubleshoot complex memory, hardware, system, and software interactions. - Analyze DDR and memory subsystem behavior, including initialization, training, configuration, performance, and error handling. - Review system architectures, schematics, logs, debug data, and technical documentation to isolate root causes and resolve issues. - Support integration and debug of CXL, PCIe, and other high-speed interfaces.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. - Typically 8+ years of relevant industry experience. - Significant hands-on experience with DDR/DRAM and memory subsystems in server, datacenter, SoC, controller, semiconductor, or related computing environments. - Strong understanding of memory architecture and the interaction between memory, CPUs/SoCs, controllers, and platform components. - Experience with memory bring-up, debug, validation, integration, or system-level troubleshooting. - Experience working with hardware, systems, validation, product, or customer engineering teams.
Nice to have
- Experience with CXL or CXL memory. - Experience with PCIe or other high-speed interconnects. - Hands-on firmware or platform software development and debugging, particularly with C/C++. - Experience with BIOS, UEFI, BMC, OpenBMC, or platform firmware. - Knowledge of memory RAS, ECC, PPR, patrol scrubbing, or related reliability technologies. - Experience using protocol analyzers, oscilloscopes, logic analyzers, or other hardware debug equipment. - Experience working with OEMs, ODMs, hyperscalers, or semiconductor customers.
Skills: firmware engineering, customer-facing, CXL Smart Memory Controllers, PCIe/CXL, DDR4/DDR5 DRAM, firmware bring-up, validation
This role has been open 178 days — well above the 60-day median for Applications FAE roles.
Applications FAE · Serdes Highspeed
|
Open roles in category
92
|
Median days open
60 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (92 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 92 |
| Median days open | 71 d | 60 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: firmware engineering, customer-facing, CXL Smart Memory Controllers, PCIe/CXL, DDR4/DDR5 DRAM, firmware bring-up
Who's hiring in this category
- Astera Labs (this employer) · 16 open roles · median 71 d
- Synopsys · 15 open roles · median 39 d
- Keysight Technologies · 11 open roles · median 46 d
- Qualcomm · 9 open roles · median 54 d
- Microchip Technology · 7 open roles · median 45 d
- Marvell Technology · 5 open roles · median 183 d
How we counted: 92 open Applications FAE (Serdes Highspeed) roles from 23 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.