Principal Product Application Engineer - PCIe - San Jose, California, United States
$170,500 - $220,000 USD yearly
Originally posted 20 May 2026 by the employer.
Support hyperscalers, OEMs, and system builders deploying Aries PCIe Smart Retimers across AI and cloud infrastructure.
About the role
Astera Labs is seeking a Principal Product Applications Engineer to join the Aries PCIe Retimer team and serve as a technical bridge between customers and the engineering organization. In this role, you will work directly with hyperscalers, OEMs, and system builders to drive deployment and adoption of Aries Smart Retimers.
What you'll do
- Serve as the primary technical resource for customers during pre-sales evaluation and post-sales deployment of Aries PCIe retimers. - Lead root cause analysis and debugging of complex PCIe signal integrity and protocol issues across customer platforms. - Support customer lab bring-up, characterization, and validation activities while developing test plans to reproduce and resolve customer-reported issues. - Create application notes, reference designs, best practices guides, datasheets, and user guides for PCIe system implementation. - Partner with product management and engineering to translate customer feedback into product requirements and roadmap discussions. - Travel to customer sites worldwide to provide on-site technical support, conduct system integration, and drive issue resolution.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of experience in applications engineering, technical support, or system engineering roles. - Strong understanding of PCIe architecture, protocol, and electrical specifications (Gen4/Gen5/Gen6). - Hands-on experience with lab equipment including oscilloscopes, protocol analyzers, and BERT tools. - Experience debugging high-speed serial interfaces at both the physical and protocol layers. - Ability to develop and modify firmware using C to implement features, optimize performance, and resolve technical issues.
Nice to have
- Experience with PCIe retimers, redrivers, or similar connectivity components. - Familiarity with server, storage, or GPU system architectures. - Background in signal integrity analysis and simulation tools. - Scripting proficiency (Python, TCL) for test automation and data analysis. - Prior experience working directly with hyperscale or enterprise data center customers. - Track record of creating high-quality technical documentation and application notes.
Skills: pcie retimer, customer technical engagement, system-level debug, signal integrity, protocol analysis
This role has been open 158 days — well above the 61-day median for Applications FAE roles.
Applications FAE · Serdes Highspeed
|
Open roles in category
92
|
Median days open
61 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (92 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 92 |
| Median days open | 72 d | 61 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: pcie retimer, customer technical engagement, system-level debug, signal integrity, protocol analysis
Who's hiring in this category
- Astera Labs (this employer) · 16 open roles · median 72 d
- Synopsys · 15 open roles · median 40 d
- Keysight Technologies · 11 open roles · median 47 d
- Qualcomm · 9 open roles · median 55 d
- Microchip Technology · 7 open roles · median 46 d
- Marvell Technology · 5 open roles · median 184 d
How we counted: 92 open Applications FAE (Serdes Highspeed) roles from 23 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.