Principal Power and Thermal Architect - CA, Santa Clara, United States
Originally posted 28 July 2026 by the employer.
About the role
As a Principal Power and Thermal Architect in the Silicon Co-Design Group (SCG), you will scout research and industry landscapes to identify emerging system-level power and thermal co-design ideas and drive them into products across NVIDIA's roadmap. The role shapes system, platform, and datacenter features while collaborating across architecture, VLSI, software, platform, packaging, and operations teams.
What you'll do
- Architect system, platform, and datacenter-level power and thermal co-design solutions across silicon, memory, packaging, and platform partners. - Build the product differentiation case for candidate concepts across performance, power, reliability, schedule, and cost. - Lead end-to-end co-design from concept to product by driving alignment across architecture, VLSI, software, platform, packaging, and operations teams. - Direct technical solutions across workload-aware power and thermal controls, closed-loop platform telemetry, datacenter-class power compliance, platform-scale energy buffering, advanced cooling intercepts, and emerging memory co-design. - Maintain a living intercept pipeline to track candidates, productization status, decision gates, and product axes, briefing group and executive leadership on status. - Collaborate with system architects, platform and software engineers, manufacturing partners, and external researchers to bring architectures into production.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience. - 15+ years in system-level power, thermal, or related architecture. - Deep expertise in at least one area: system power management, system thermal architecture, platform energy architecture, workload-aware power and thermal controls, or memory co-design. - External technical recognition demonstrated through publications, patents, industry standards contributions, or active involvement in consortia and external technical communities. - Track record of transitioning research-grade concepts through system co-design into measurable product impact. - Demonstrated multi-functional influence in aligning cross-company teams without direct reporting authority.
This role has been open 119 days — well above the 51-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
1003
|
Median days open
51 d
|
Median salary
$155k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1003 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 52 | 1003 |
| Open roles in the wider Software, Firmware & Systems family | 997 | 6298 · 145 employers |
| Median days open | 69 d | 51 d (+18 d vs this employer) |
| Median salary (USD postings) | — | $155k |
Who's hiring in this category
- Intel Corporation · 72 open roles · median 34 d
- KLA Corporation · 63 open roles · median 48 d
- Teradyne · 61 open roles · median 34 d
- NVIDIA (this employer) · 53 open roles · median 72 d
- Applied Materials · 51 open roles · median 70 d
- AMD · 46 open roles · median 52 d
How we counted: 1003 open Hardware Systems Engineering (AI ML Hardware) roles from 104 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.