Principal Post-Silicon Validation Engineer - San Jose, California, United States
$207,000 - $230,000 USD yearly
Originally posted 20 October 2026 by the employer.
About the role
Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize silicon in the lab, and drive root-cause analysis of system-level issues.
What you'll do
- Architect and drive end-to-end post-silicon validation plans from first-silicon bring-up through characterization and production release. - Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams. - Lead lab bring-up of new silicon, including board, firmware, and software readiness. - Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary. - Characterize high-speed serial link performance, including margining, signal integrity, and compliance across process, voltage, and temperature. - Develop scalable validation automation frameworks, test content, and lab infrastructure using Python and C/C++.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization. - Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer. - Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies. - Scripting and programming skills in Python and/or C/C++ for test automation. - Ability to debug complex hardware and firmware issues to root cause.
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field. - Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products. - Experience with SerDes characterization, equalization tuning, and link margining. - Track record of taking multiple products from first silicon to volume production.
This role has been open 0 days — well below the 68-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
117
|
Median days open
68 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (117 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 117 |
| Open roles in the wider Silicon Validation & Test family | 21 | 2229 · 113 employers |
| Median days open | 64 d | 68 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 41 d
- AMD · 15 open roles · median 67 d
- NVIDIA · 15 open roles · median 74 d
- Graphcore · 10 open roles · median 125 d
- Amazon · 6 open roles · median 44 d
- Micron Technology · 5 open roles · median 215 d
How we counted: 117 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.