Principal Post-Silicon Validation Engineer - San Jose, California, United States
$180,000 USD yearly
Originally posted 18 August 2026 by the employer.
SambaNova is seeking a Principal Post-Silicon Validation Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale® platform.
About the role
SambaNova is seeking a Principal Post-Silicon Validation Engineer to own post-silicon bring-up, debug, and validation of high-speed IO and memory subsystems within the DataScale® platform.
What you'll do
- Own post-silicon bring-up and validation of high-speed IO and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis.
- Lead system-level debug to root cause complex issues spanning silicon, board, and software layers.
- Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule.
- Partner with system and customer engineering teams on product validation, deployment, and RMA debug.
- Own validation sign-off for product release against stability, performance, and field reliability targets.
- Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage.
What you'll need
- M.S. in Electrical Engineering, Computer Science, or a related field.
- 7+ years of experience in post-silicon validation or system bring-up.
- Experience with two or more high-speed IO or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe.
- Proven ability to lead cross-functional debug efforts to root cause and closure.
- Strong analytical skills for test development and data analysis.
- Proficiency in scripting such as Python and bash.
Nice to have
- Deep understanding of high-speed SerDes training and adaptation.
- Experience with mixed-signal IO design and validation.
- Hands-on lab experience with oscilloscopes, protocol analyzers, and BERTs.
- Experience with optical interconnect.
- Ability to read and debug C/C++.
This role has been open 59 days — below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
118
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (118 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 118 |
| Open roles in the wider Silicon Validation & Test family | 4 | 2226 · 113 employers |
| Median days open | 59 d | 64 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 37 d
- AMD · 15 open roles · median 63 d
- NVIDIA · 15 open roles · median 70 d
- Graphcore · 10 open roles · median 121 d
- Amazon · 6 open roles · median 40 d
- Micron Technology · 5 open roles · median 211 d
How we counted: 118 open Post-Silicon Validation (Design Verification) roles from 30 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.