Principal PLL Design Engineer - Irvine, CA or San Jose, CA, United States

Originally posted 6 April 2026 by the employer — open 157 days.

About the role

This role involves the architecture and design of advanced clocking circuits for optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems.

What you'll do

• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range.
• Architect, design, and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre.
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization, and device-level noise optimization.
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies.
• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies.

What you'll need

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
• Extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes).
• Deep understanding of phase noise analysis, VCO design, LDOs, and supporting circuitry associated with PLLs.
• Proficient in Cadence Virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling.

Skills: PLL topologies, VCOs, Cadence Virtuoso, Spectre, transistor level