Principal Place and Route (PnR) Engineer
Develop and tune partitioning, placement, and routing algorithms mapping dataflow graphs onto the Reconfigurable Dataflow Unit (RDU).
Originally posted 29 October 2026 by the employer.
About the role
You will develop and tune partitioning, placement, and routing algorithms that map customer workloads onto SambaNova's Reconfigurable Dataflow Unit (RDU). Working with compiler teams, hardware architects, and performance engineers, you will model hardware constraints and trace throughput gaps back to mapping decisions.
What you'll do
- Develop partitioning, placement, and routing algorithms that satisfy hardware resource constraints while maintaining practical compile times.
- Tune PnR results for target workloads, including LLM inference across various batch sizes and concurrency levels.
- Model hardware constraints and architecture features in solvers and heuristics as the chip evolves.
- Analyze compiled output with performance engineers to trace throughput gaps back to mapping decisions.
- Build infrastructure for prototyping, regression testing, and deployment of PnR changes.
- Collaborate with compiler and hardware teams to define interfaces and resource models.
What you'll need
- M.S. or Ph.D. in Computer Science, Computer Engineering, or a related field.
- 3+ years of experience developing optimization or graph algorithms in industry or research.
- Expert knowledge of graph algorithms, partitioning algorithms, combinatorial optimization, or MILP solvers.
- Strong proficiency in C/C++ and familiarity with Python.
- Experience designing large, highly parallel, performance-sensitive systems.
- Experience solving NP-hard problems in practice using heuristics, approximation, or pruned exact methods.
Nice to have
- Experience with place and route for FPGAs, CGRAs, or other spatial architectures.
- Experience with ML compilers such as MLIR, LLVM, TVM, or XLA.
- Experience with simulated annealing, constraint programming, or SAT/SMT solvers.
- Familiarity with LLM inference stacks such as vLLM and PyTorch.
- Publications at venues such as FPGA, DAC, ICCAD, or MLSys.
Skills: partitioning, placement and routing, graph algorithms, MILP, C++
More semiconductor jobs: EDA tools engineer jobs · Austin jobs
This role has been open 0 days — well below the 63-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
745
|
Median days open
63 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SambaNova | All employers we track in this specialty (745 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 745 |
| Open roles in the wider Physical Implementation family | 3 | 1545 · 112 employers |
| Median days open | 0 d | 63 d (−63 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: partitioning, placement and routing, graph algorithms, MILP, C++
Who's hiring in this category
- Cadence Design Systems · 158 open roles · median 154 d
- Synopsys · 64 open roles · median 47 d
- Micron Technology · 50 open roles · median 43 d
- GlobalFoundries · 40 open roles · median 30 d
- Qualcomm · 36 open roles · median 80 d
- Renesas Electronics · 36 open roles · median 7 d
How we counted: 745 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.