Principal Physical Design Engineer - San Jose, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 21 September 2026 by the employer — open 0 days.
Celero Communications is developing 2nm coherent DSP silicon.
About the role
This role involves leading the transformation of complex circuit designs into high-quality, manufacturable silicon, driving all aspects of the physical implementation flow. You will contribute to the successful tape-out of 2nm coherent DSP silicon.
What you'll do
- Own physical implementation of SoCs or complex digital blocks (RTL-to-GDSII execution).
- Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
- Resolve timing, congestions, and EM/IR issues.
- Run Static Timing Analysis (STA) and physical verification; fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
- Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
- Partner with architects, logic designers, and analog design teams for tapeout readiness.
What you'll need
- 7+ years of relevant ASIC physical design experience.
- Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
- Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
- Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.
Skills: RTL-to-GDSII, floor-planning, power grid design, clock tree synthesis, Static Timing Analysis, DRC, LVS
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
606
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (606 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 606 |
| Open roles in the wider Physical Implementation family | 8 | 1392 · 107 employers |
| Median days open | 18 d | 61 d (−43 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL-to-GDSII, floor-planning, power grid design, clock tree synthesis, Static Timing Analysis, DRC
Who's hiring in this category
- Qualcomm · 111 open roles · median 43 d
- Broadcom · 38 open roles · median 71 d
- NVIDIA · 38 open roles · median 46 d
- AMD · 35 open roles · median 41 d
- Synopsys · 27 open roles · median 60 d
- Renesas Electronics · 25 open roles · median 48 d
How we counted: 606 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.