Principal Physical Design Engineer, Methodology - San Jose, California, United States
$185,000 - $240,000 USD yearly
Originally posted 22 July 2026 by the employer.
About the role
Define, develop, and maintain the reusable physical design flows and automation infrastructure that the entire physical design team relies on. This on-site role focuses on building the RTL-to-GDSII flow across multi-vendor toolchains to improve PPA and schedule predictability for complex SoCs.
What you'll do
- Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR. - Own the end-to-end RTL-to-GDSII flow infrastructure across Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, ICC2, PrimeTime, StarRC) toolchains. - Evaluate and qualify new EDA tool features, foundry enablement kits, and DRC/LVS/extraction runsets to ensure consistency with foundry requirements. - Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs. - Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across concurrent tapeout programs. - Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below). - Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows. - Hands-on experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains. - Scripting proficiency in Python, Tcl, and/or Perl for flow development and automation. - Experience building and maintaining multi-corner/multi-mode analysis infrastructure and integrating foundry design rules and enablement kits.
Nice to have
- Knowledge of agentic AI solutions for EDA automation. - Experience with CI/CD integration for physical design flows. - Familiarity with compute farm management and job scheduling optimization. - Knowledge of advanced packaging or multi-die integration flows. - Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Skills: RTL-to-GDSII flow, synthesis, place-and-route, STA, EMIR
This role has been open 89 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 659 |
| Open roles in the wider Physical Implementation family | 22 | 1441 · 109 employers |
| Median days open | 121 d | 61 d (+60 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL-to-GDSII flow, synthesis, place-and-route, STA, EMIR
Who's hiring in this category
- Qualcomm · 119 open roles · median 46 d
- AMD · 63 open roles · median 25 d
- Intel Corporation · 37 open roles · median 12 d
- Synopsys · 37 open roles · median 33 d
- NVIDIA · 36 open roles · median 71 d
- Broadcom · 30 open roles · median 98 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.