$143,800 - $230,000 USD yearly
Originally posted November 13, 2026 by the employer.
About the role
Broadcom’s ASIC Products Division (APD) is looking for a Principal Physical Design Engineer to lead physical design implementation tasks for high-performance networking, AI/ML accelerators, and custom cloud ASICs. You will drive complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across deep sub-micron nodes (N5/N3/N2/A14).
What you'll do
- Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus.
- Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks.
- Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk.
- Deploy AI automation within the APD flows to improve efficiency and reduce runtime.
What you'll need
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 12+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
- Direct experience executing tape outs in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency in Cadence Innovus for P&R.
- High proficiency in Synopsys PrimeTime or Cadence Tempus for Timing/STA.
- Experience with StarRC / QRC, RedHawk for extraction & IR/EM, and Siemens Calibre for DRC/LVS.
Nice to have
- Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS).
- Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating).
Skills: Innovus, Place and Route, floorplanning, CTS, STA, PrimeTime
More semiconductor jobs: Broadcom jobs · Physical design jobs
First seen in our index 1 day ago, well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
753
|
Median days since first seen
62 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (753 roles · 90 employers) |
|---|---|---|
| Open roles in this specialty | 53 | 753 |
| Open roles in the wider Physical Implementation family | 58 | 1699 · 121 employers |
| Median days since first seen | 24 d | 62 d (+38 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: Innovus, Place and Route, floorplanning, CTS, STA, PrimeTime
Who's hiring in this category
- Qualcomm · 119 open roles · median 66 d
- AMD · 66 open roles · median 45 d
- Broadcom (this employer) · 53 open roles · median 24 d
- NVIDIA · 46 open roles · median 85 d
- Synopsys · 44 open roles · median 43 d
- Apple · 32 open roles · median 8 d
How we counted: 753 open Physical Design (Physical Design) roles from 90 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.