Principal Packaging Engineer - Santa Clara, CA, United States
$200,000 - $500,000 USD yearly
Originally posted 15 July 2026 by the employer.
Own package architecture and development for Velaura’s SoCs.
About the role
This role will own package architecture and development for Velaura’s SoCs, leading packaging from concept through production.
What you'll do
- Own package architecture from concept through production for Velaura SoCs.
- Partner with architecture and silicon teams to co-optimize package, die, board, and system design.
- Drive package technology selection, including flip-chip, advanced substrates, fan-out, and multi-die integration approaches.
- Lead package design, bump planning, substrate definition, escape routing, and assembly interactions with OSAT and substrate vendors.
- Own package-level signal integrity and power integrity planning for high-speed interfaces including LPDDR, PCIe, Ethernet, and other high-speed I/O.
- Collaborate on thermal architecture, mechanical integration, reliability, DFM, and qualification.
What you'll need
- Deep experience developing advanced semiconductor packages for high-performance SoCs.
- Strong understanding of package architecture, substrate technologies, bumping, assembly flows, and manufacturing.
- Experience co-optimizing package design with silicon, board, SI/PI, thermal, and mechanical teams.
- Hands-on experience with signal integrity, power integrity, thermal, and reliability considerations in advanced packages.
- Ability to balance technical excellence with cost, yield, manufacturability, and schedule.
Nice to have
- Advanced packaging technologies including chiplets, 2.5D integration, silicon bridges, or heterogeneous integration.
- HBM integration and high-bandwidth memory package architecture.
- Advanced process nodes (N3, N2).
- Experience working with foundries, OSATs, and substrate vendors.
- Experience in an early-stage semiconductor company.
Skills: package architecture, multi-die integration, signal integrity, power integrity, advanced substrates
This role has been open 84 days — well above the 47-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
69
|
Median days open
47 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (69 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 69 |
| Median days open | 84 d | 47 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Skills observed across this category: package architecture, multi-die integration, signal integrity, power integrity, advanced substrates
Who's hiring in this category
- Micron Technology · 10 open roles · median 170 d
- AMD · 9 open roles · median 45 d
- NVIDIA · 6 open roles · median 41 d
- Marvell Technology · 5 open roles · median 38 d
- Broadcom · 4 open roles · median 141 d
- GlobalFoundries · 4 open roles · median 109 d
How we counted: 69 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 25 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.