Principal Package Engineer - Palo Alto
$180,000 - $270,000 USD yearly
Originally posted 1 October 2026 by the employer.
Delos Data is building foundational technology for high-performance AI accelerators.
About the role
This role focuses on architecting and delivering advanced multi-die IC packages for high-performance AI accelerators, with a focus on package architecture, substrate design, and manufacturability.
What you'll do
- Select and design optimal multi-die package types (MCM, 2.5D, 3D, fan-out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.
- Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
- Define substrate stack-ups, bump pitch, ball pitch, routing, via structures, and material choices.
- Perform high-speed signal escaping, routing and power distribution network design.
- Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.
- Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system-level needs.
- Support package-level bring-up, failure analysis, debug and qualification.
What you'll need
- B.S./M.S. in Electrical Engineering or related field.
- Experience with multi-die package design and UCIe (AP/SP) integration.
- Understanding of substrate materials, stack-ups, and mechanical constraints.
- Familiarity with SI/PI concepts.
- Experience managing packaging subcontractors.
- Experience interfacing with TSMC/OSAT for bumping and packaging options.
Nice to have
- Knowledge of package modeling tools (HFSS, Sigrity, or similar).
Skills: multi-die package, UCIe, CoWoS, SI/PI, substrate
This role has been open 2 days — well below the 93-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
42
|
Median days open
93 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Delos Data | All employers we track in this specialty (42 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 42 |
| Median days open | 2 d | 93 d (−91 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: multi-die package, UCIe, CoWoS, SI/PI, substrate
Who's hiring in this category
- Marvell Technology · 5 open roles · median 32 d
- Qualcomm · 5 open roles · median 96 d
- Intel Corporation · 4 open roles · median 20 d
- Micron Technology · 4 open roles · median 143 d
- NVIDIA · 4 open roles · median 55 d
- GlobalFoundries · 3 open roles · median 23 d
How we counted: 42 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 20 employers tracked in the SemiconductorJobs index, counted 4 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.