Principal Package Design Engineer - Tempe, United States
Originally posted 23 July 2026 by the employer. Relisted by the employer on 21 October 2026.
Focus on package development for power SiP/modules, flip-chip LGA, and embedded die/capacitors.
About the role
Design and develop package and interconnect methods for Renesas packaging needs in Power SiP/modules, flip-chip LGA, multi-chip modules with substrate or embedded die/capacitor, and power device packaging. This role focuses on package technologies qualification for consumer, industrial, and automotive power applications.
What you'll do
- Benchmark, select, and qualify materials, assembly processes, and assembly subcontractors (OSAT) or contract manufacturers (CM). - Partner with OSAT/CM partners to run DOE, optimize processes, establish process specifications, and resolve process integration issues. - Collaborate with Product groups and Reliability teams to qualify new packages and processes, establishing package design rules and production controls. - Oversee smooth transitions into production, implement ramp-up monitoring, and resolve early-stage production process issues. - Participate in packaging roadmap development and maintain technical expertise in power SiP/modules, wafer level packaging, and flip-chip interconnects in LGA. - Address internal and external customer complaints in coordination with Marketing, Product, Quality, and Operations teams.
What you'll need
- Doctorate, Master’s, or Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical, or Materials Engineering. - 10-15 years of relevant package development experience emphasizing power SiP/module, wafer level, and flip-chip LGA packaging. - Deep understanding of power SiP/modules containing substrates or embedded die/capacitors. - Solid working knowledge of assembly processes, package qualification methods, SPC, and statistical analysis software.
Nice to have
- Knowledge of Cu FSM/BGBM technologies.
Skills: hermetic packaging, plastic package technologies, IC assembly processes, package qualification, OSAT partners
This role has been open 90 days — well above the 57-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
212
|
Median days open
57 d
|
Median salary
$165k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (212 roles · 43 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 212 |
| Open roles in the wider Process, Fab & Equipment family | 197 | 10066 · 107 employers |
| Median days open | 37 d | 57 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $165k |
Skills observed across this category: hermetic packaging, plastic package technologies, IC assembly processes, package qualification, OSAT partners
Who's hiring in this category
- Infineon Technologies · 28 open roles · median 43 d
- Renesas Electronics (this employer) · 27 open roles · median 36 d
- Micron Technology · 21 open roles · median 103 d
- onsemi · 15 open roles · median 26 d
- Monolithic Power Systems · 11 open roles · median 215 d
- Intel Corporation · 9 open roles · median 106 d
How we counted: 212 open Packaging Engineering (Packaging) roles from 43 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.