Principal NoC IP Micro-Architect - San Jose, California, United States
$209,500 - $299,200 USD yearly
Originally posted 15 July 2026 by the employer.
About the role
As a Principal NoC IP Micro-Architect, you will lead the end-to-end architecture, microarchitecture, RTL design, and technical direction of scalable Network on Chip (NoC) IP solutions integrated into FPGA platforms. You will work across architecture, design, verification, software, and physical design teams to optimize interconnect solutions for power, performance, and area (PPA).
What you'll do
- Develop logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and FPGA subsystems integrated into full chip designs. - Define architecture and microarchitecture features, specify system requirements, and design logic diagrams and implementation code. - Apply RTL implementation techniques to meet power, performance, and area (PPA) targets in collaboration with physical implementation teams. - Deliver software models for device-level bring-up, including user-visible functionality, timing, and power. - Utilize design methodology and EDA tools including timing constraints verification, RTL lint, CDC, RDC, and DFT. - Review verification plans, resolve failing RTL tests, and technically guide the NoC engineering team across project milestones.
What you'll need
- Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related experience. - 10+ years of experience in the development of Network on Chip IPs. - 10+ years of experience in SystemVerilog, VCS or Synopsys simulators, Lint, and Synthesis. - 10+ years of experience programming with C, C++, Perl, Python, TCL, or Unix Shell script.
Nice to have
- 10+ years of experience in FPGA design and programming. - 10+ years of experience in RTL validation. - 5+ years of experience utilizing AI within the engineering development process.
This role has been open 96 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1045
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Altera | All employers we track in this specialty (1045 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 1045 |
| Open roles in the wider Digital Design & Verification family | 22 | 3244 · 116 employers |
| Median days open | 95 d | 62 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 148 open roles · median 58 d
- Synopsys · 85 open roles · median 34 d
- AMD · 72 open roles · median 40 d
- Analog Devices · 49 open roles · median 52 d
- NVIDIA · 42 open roles · median 62 d
- NXP Semiconductors · 42 open roles · median 88 d
How we counted: 1045 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.