Principal Mixed Analog Design Engineer - Irvine, California, United States
$170,000 - $210,000 USD yearly
Originally posted 12 October 2026 by the employer.
This role involves architecting and designing high-performance analog and mixed-signal circuits that anchor SerDes, PHY, and high-speed I/O.
About the role
As a Principal Mixed Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O.
What you'll do
- Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.
- Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.
- Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.
- Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering.
- Define and execute test plans to correlate silicon performance against design targets.
- Set analog design methodology, review standards, and best practices across the team.
- Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.
- Mentor and guide junior engineers, elevating the technical capability of the analog organization.
What you'll need
- MS or PhD in Electrical Engineering or a related field.
- 8+ years of experience in analog and mixed-signal integrated circuit design.
- Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.
- Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.
Nice to have
- Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.
- Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.
- Familiarity with silicon debug, ATE test development, and design-for-test techniques.
- Experience mentoring engineers and leading technical design reviews.
Skills: SerDes, PHY, high-speed I/O, PLLs, FinFET
This role has been open 2 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 7 | 1412 · 104 employers |
| Median days open | 108 d | 78 d (+30 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: SerDes, PHY, high-speed I/O, PLLs, FinFET
Who's hiring in this category
- Synopsys · 31 open roles · median 30 d
- AMD · 30 open roles · median 39 d
- Cadence Design Systems · 19 open roles · median 188 d
- Qualcomm · 19 open roles · median 57 d
- Micron Technology · 14 open roles · median 53 d
- Apple · 12 open roles · median 16 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.