Principal Logic Design Engineer - UALink IP/Subsystem - Bengaluru, Karnataka, India
Originally posted 17 September 2026 by the employer — open 0 days.
About the role
This role involves leading RTL and microarchitecture development for UALink-based IP/subsystems.
What you'll do
- Lead architecture and RTL development for UALink IP/subsystems.
- Translate protocol and system requirements into scalable hardware architecture.
- Design high-bandwidth, low-latency data paths and control logic.
- Develop mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Define interfaces between UALink and other SoC/interconnect components.
- Develop and review SystemVerilog RTL.
- Drive design optimization for performance, power, area, and latency.
- Work closely with verification, physical design, SoC integration, and firmware teams.
What you'll need
- Strong experience in RTL and microarchitecture development.
- Experience with high-speed interconnects and/or coherent fabrics.
- Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
- Proficiency in SystemVerilog/Verilog.
- Strong understanding of CDC, reset architecture, performance, and hardware design methodology.
Nice to have
- Direct UALink experience.
- Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
- Experience in AI/accelerator or high-performance compute systems.
Skills: RTL development, microarchitecture, SystemVerilog, high-performance interconnect, SoC/IP design
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
921
|
Median days open
62 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (921 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 921 |
| Open roles in the wider Digital Design & Verification family | 52 | 3004 · 115 employers |
| Median days open | 38 d | 62 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: RTL development, microarchitecture, SystemVerilog, high-performance interconnect, SoC/IP design
Who's hiring in this category
- Qualcomm · 134 open roles · median 58 d
- AMD · 60 open roles · median 67 d
- Synopsys · 56 open roles · median 31 d
- NXP Semiconductors · 53 open roles · median 64 d
- NVIDIA · 49 open roles · median 50 d
- Analog Devices · 38 open roles · median 75 d
How we counted: 921 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.