Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes - Milpitas, United States
Originally posted 1 July 2026 by the employer — open 70 days.
About the role
This role involves owning the architectural direction of ultra high-speed SerDes platforms targeting 448G per lane and emerging post-448G standards, spanning electrical and optical interfaces. This includes driving end-to-end link architecture, DSP algorithm design, and ADC/DAC-based transceiver partitioning for ultra high-speed SerDes IP.
What you'll do
- Define DSP and system architecture for 448G and post-448G SerDes IP across electrical and optical interfaces.
- Lead technical engagement with hyperscale, AI accelerator, and optical module customers, representing the company in OIF CEI and IEEE 802.3 standards activities.
- Build and maintain MATLAB/Python models of the full link across electrical and optical media, including channel response, impairments, jitter, crosstalk, and FEC performance.
- Own the DSP pipeline across electrical and optical paths, including FFE, DFE, MLSE/MLSD, CTLE-DSP partitioning, and adaptive equalization.
- Drive wordlength optimization, parallelism, and pipelining strategies for multi-hundred-GSps datapaths, and float-to-fixed methodology.
- Translate DSP reference models into hardware-friendly architectures with bit-true/cycle-accurate alignment.
What you'll need
- Graduate degree in EE, Communications, or Signal Processing.
- 10+ years in high-speed SerDes or wireline/optical link DSP/systems architecture, with direct exposure to 112G/224G silicon.
- Proven ownership of end-to-end link budgets with cascaded impairment analysis.
- Expertise in PAM4/PAM6 and coherent wireline/optical signaling, advanced equalization (FFE, DFE, MLSE/MLSD), optical DSP (CD/PMD compensation), and adaptive algorithms.
- Experience with KP4 and soft-decision FEC, high-speed ADC/DAC architectures, CDR and timing recovery, and jitter/crosstalk/SI modeling.
- Familiarity with OIF CEI (CEI-224G, CEI-448G), IEEE 802.3 high-speed Ethernet, and relevant optical standards.
Nice to have
- PhD strongly preferred.
- Strong communication skills with VP- and CTO-level stakeholders at hyperscale and module customers.
Skills: ultra high-speed SerDes, DSP algorithm design, ADC/DAC-based transceiver, end-to-end link architecture, PAM/multi-level signaling, FEC
This role has been open 70 days — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Omni Design Technologies | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 3 | 217 |
| Median days open | 85 d | 91 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ultra high-speed SerDes, DSP algorithm design, ADC/DAC-based transceiver, end-to-end link architecture, PAM/multi-level signaling, FEC
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.