Principal IC Analog / Mixed Signal Design Engineer - MA, Wilmington, United States

Originally posted 3 September 2026 by the employer.

About the role

This role involves leading analog and mixed-signal circuit design from architecture through silicon validation within the Data Center & Energy (DCE) group. The position focuses on mixed-signal SoCs combining precision analog front-ends, high-speed data converters, and embedded processing in advanced FinFET process technologies.

What you'll do

• Own analog architecture and circuit design for complex mixed-signal SoC subsystems.
• Perform transistor-level design, simulation, and optimization in deep submicron FinFET processes.
• Drive system-level analog/digital partitioning decisions and define/validate specifications.
• Lead mixed-signal verification including behavioral modeling, co-simulation with digital, and corner/Monte Carlo analysis.
• Support silicon bring-up, characterization, and debug, collaborating with layout, DFT, and test engineering.
• Provide technical mentorship, lead design reviews, and establish reusable IP and best practices.

What you'll need

• BSEE with 12+ years of analog/mixed-signal IC design experience.
• Demonstrated track record of silicon-proven designs in deep submicron FinFET processes.
• Deep understanding of device physics, mismatch, leakage management, and reliability at advanced nodes.
• Experience designing precision analog circuits: voltage references, regulators, ADC front-ends, bias generators, comparators.
• Proficiency with industry EDA tools (Cadence Virtuoso, Spectre, AMS simulation environments).
• Experience taking designs from specification through layout, tapeout, silicon bring-up, and production release.

Nice to have

• MSEE or PhD preferred.
• Experience mentoring engineers and leading design reviews.
• Familiarity with DFT, production test, and design-for-manufacturability practices in advanced CMOS.

Skills: analog architecture, circuit design, precision voltage sensing, high-speed data conversion, power regulation, FinFET processes