Principal High-Speed I/O Architect (PCIe, CXL, UA Link) - San Jose, California, United States
$262,700 - $355,400 USD yearly
Originally posted 6 August 2026 by the employer — open 35 days.
About the role
This role involves defining and designing innovative on-chip interconnect architectures for scalable SoC platforms.
What you'll do
- Architect high-speed interconnect subsystems including PCIe, CXL, and UA Link, and define coherent and non-coherent communication architectures.
- Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies.
- Lead early architecture engagements with customers, delivering implementation-ready specifications.
- Optimize PCIe/CXL/UA Link subsystem behavior, bandwidth, latency, and overall system efficiency.
- Develop SoC architecture integrating Arm IP and high-speed I/O subsystems.
- Support use-case exploration, workload analysis, and performance modeling.
What you'll need
- 8+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
- Expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die or chiplet connectivity, and host/device integration.
- Track record collaborating with performance, power, and physical design teams on the PCIe, CXL, and UA Link stack.
- Knowledge in heterogeneous compute, PCIe/CXL/UA Link subsystem design, security, caching, memory systems.
- Bachelor's or Master's degree (or equivalent) in Electrical or Computer Engineering with 10+ years of experience in semiconductor architecture, design, or related roles.
Nice to have
- Ability to thrive in dynamic environments with shifting priorities.
- Constructive, strategic approach to challenge and improve status quo.
- Track record of delivering complex projects on time and to spec.
Skills: PCIe, CXL, UA Link, high-speed interconnect, coherent communication, subsystem roadmaps
This role has been open 176 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 1 | 217 |
| Median days open | 176 d | 91 d (+85 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: PCIe, CXL, UA Link, high-speed interconnect, coherent communication, subsystem roadmaps
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.