Principal High-Speed I/O Architect (PCIe, CXL, UA Link) - Austin, Texas, United States
$249,900 - $338,100 USD yearly
Originally posted 16 July 2026 by the employer.
About the role
The Principal High-Speed I/O Architect defines and designs on-chip interconnect architectures—coherent and non-coherent—for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets. The role focuses on high-speed interconnect subsystems including PCIe, CXL, and UA Link.
What you'll do
- Architect high-speed interconnect subsystems—including PCIe, CXL, and UA Link—and define coherent and non-coherent communication architectures across silicon products. - Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies in partnership with SoC architecture and core technology teams. - Lead early architecture engagements with customers, shaping system requirements and delivering implementation-ready specifications. - Collaborate with performance, power, and physical design teams to optimize PCIe/CXL/UA Link subsystem behavior, bandwidth, latency, and overall system efficiency. - Develop SoC architecture integrating Arm IP and high-speed I/O subsystems to meet compute, memory, and interconnect performance targets. - Partner with software, firmware, and platform teams to optimize solutions across hardware, drivers, and system software, supporting workload analysis and performance modeling.
What you'll need
- Bachelor’s or Master’s degree (or equivalent) in Electrical or Computer Engineering with 10+ years of experience in semiconductor architecture, design, or related roles. - 8+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures. - Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die or chiplet connectivity, and host/device integration. - Track record collaborating with performance, power, and physical design teams on the PCIe, CXL, and UA Link stack. - Strong knowledge in heterogeneous compute, PCIe/CXL/UA Link subsystem design, security, caching, and memory systems. - Demonstrated communication and leadership skills with the ability to influence executive stakeholders and multi-functional teams.
Skills: PCIe, CXL, UA Link, coherent communication, interconnect subsystems, SoC architecture
This role has been open 96 days — well above the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
475
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (475 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 475 |
| Open roles in the wider Digital Design & Verification family | 104 | 3261 · 116 employers |
| Median days open | 118 d | 77 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: PCIe, CXL, UA Link, coherent communication, interconnect subsystems, SoC architecture
Who's hiring in this category
- Qualcomm · 76 open roles · median 87 d
- NVIDIA · 55 open roles · median 70 d
- Apple · 38 open roles · median 13 d
- AMD · 34 open roles · median 63 d
- Arm Holdings (this employer) · 27 open roles · median 118 d
- Micron Technology · 22 open roles · median 110 d
How we counted: 475 open SoC/Chip Architecture (SOC Architecture) roles from 66 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.