Principal High Speed Clocking Design Engineer

Originally posted 31 July 2026 by the employer — open 41 days.

This role focuses on future DDR, LPDDR related product IPs.

About the role

This role involves the definition, specification, system simulation, and implementation of future DDR, LPDDR related product IPs, with a focus on high-speed analog and digital blocks. The primary focus is on circuit architecture and design of critical high-speed clocking blocks like PLL, VCO, and PI for memory design.

What you'll do

• Own critical clocking blocks such as PLL, VCO, PI.
• Design, simulate, and characterize high-performance and high-speed circuits.
• Create high-level models for design tradeoff analysis and behavioral models for verification simulations.
• Work with digital/system teams to define architecture and design plans.
• Create floor plan and collaborate with the layout team for post-extraction performance.
• Document analysis and simulation to show design achieves critical electrical, timing parameters, and pre-silicon verification flow.

What you'll need

• MS EE with 7+ years or PhD EE with 5+ years’ experience in analog/mixed-signal circuit design.
• Prior design experience in ultra-low noise PLL designs supporting sub-pico second high-frequency jitter.
• Prior experience in ultra-noise, high-linearity, low-power PI architectures.
• Prior experience in memory clock tree designs.
• Knowledge of DDR5 specifications.
• Solid knowledge of design principles for practical design tradeoffs.

Nice to have

• Prior experience in DLL architectures.
• Prior experience with data buffer architectures.
• Prior experience with bandwidth peaking approaches.
• Experience in working in R&D and future technology development projects.

Skills: PLL, VCO, PI, analog/mixed signal designs, DDR5, DLL