Principal High-Speed Analog Layout Design Engineer - Ottawa, Ontario, Canada
Originally posted 9 September 2026 by the employer.
This role focuses on the layout design of complex analog and mixed-signal IP blocks for advanced optical communication systems.
About the role
This role involves driving the layout design of complex analog and mixed-signal IP blocks that are at the heart of advanced optical communication systems. You will lead layout development of critical blocks such as ADCs, DACs, and PLLs.
What you'll do
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification.
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability.
- Mentor and guide junior layout engineers/contractors.
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre).
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing.
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence.
What you'll need
- 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
- Proven track record of top-level integration IP layout macros and preparing IPs for handoff to Physical Design.
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes.
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16).
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE), and their impact on circuit performance.
- Expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization.
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design.
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools.
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.
- Experience using revision control systems for layout design management.
Nice to have
- Exposure to optical or high-speed analog interfaces.
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization.
- Proven ability to collaborate with international teams (U.S., Canada, Argentina).
Skills: physical layout design, ADCs, DACs, PLLs, Cadence Virtuoso, FinFET technologies
This role has been open 48 days — well above the 35-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
75
|
Median days open
35 d
|
Median salary
$164k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (75 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 75 |
| Open roles in the wider Analog & Mixed-Signal family | 13 | 1461 · 106 employers |
| Median days open | 59 d | 35 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $164k |
Skills observed across this category: physical layout design, ADCs, DACs, PLLs, Cadence Virtuoso, FinFET technologies
Who's hiring in this category
- Analog Devices · 9 open roles · median 35 d
- Celero (this employer) · 8 open roles · median 59 d
- Renesas Electronics · 7 open roles · median 24 d
- Marvell Technology · 6 open roles · median 31 d
- onsemi · 6 open roles · median 27 d
- Infineon Technologies · 5 open roles · median 12 d
How we counted: 75 open Analog IC Design (Analog Layout) roles from 24 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.