Principal HIG ESD and Latch-up Engineer- HBM - TPG - Hsinchu, Taiwan
Originally posted 29 September 2026 by the employer.
About the role
This role involves defining and owning chip-level and IP-level ESD and latch up strategies for Micron’s HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces.
What you'll do
- Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces.
- Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards.
- Enable ESD protection circuits and latch up safe layout practices across designs and technologies.
- Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results.
- Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams.
What you'll need
- Master’s degree or Ph.D. in Electrical Engineering or equivalent industry experience.
- Strong fundamentals in ESD physics, latch up mechanisms, and advanced CMOS devices.
- Hands-on experience with ESD protection circuits and latch up prevention techniques.
- Familiarity with JEDEC and ESDA standards, including HBM, CDM, and JESD78.
Nice to have
- Experience supporting ESD and latch up sign-off for advanced DRAM or HBM products.
- Knowledge of SCR-based clamps, distributed ESD networks, and rail-based strategies.
- Experience working directly with foundry ESD and latch up teams.
- Proven ability to mentor engineers and influence design methodology across teams.
Skills: ESD, latch up, HBM DRAM, JEDEC, silicon validation
This role has been open 6 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: ESD, latch up, HBM DRAM, JEDEC, silicon validation
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.