Principal FPGA Emulation Engineer (Semiconductor Industry)

Originally posted 11 November 2026 by the employer.

About the role

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own FPGA-based platforms that emulate mixed-signal power ASICs before silicon. You will partner with silicon RTL and DSP architects to validate real-time digital, mixed-signal, and power-control architectures pre-silicon.

What you'll do

• Partner with silicon RTL and DSP architects to bring ASIC designs up on FPGA platforms, turning architectural intent into real-time emulation platforms.
• Adapt ASIC RTL for FPGA emulation while preserving functional equivalence, handling clock-gating conversion, memory/SRAM macro mapping, reset schemes, tri-state/bus conversion, and modeling analog/mixed-signal blocks.
• Map designs onto the FPGA fabric to hit emulation speed, steering resource inference for DSP/multiplier slices, block versus distributed memory, clocking, and pipelining.
• Build real-time environments around the digital core by modeling or interfacing to analog and power stages such as ADC/DAC/PWM, gate drivers, and converter models.
• Develop pre-silicon debug and visibility flows using logic analysis, long-run waveform capture, triggering, and assertions to support firmware and software co-development.
• Define emulation methodology, RTL/FPGA-ability guidelines, flows, and automation scripts using TCL and Python while providing technical leadership and mentoring.

What you'll need

• Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs.
• Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL.
• Deep understanding of FPGA internal architecture and primitives—including DSP/multiplier slices, block and distributed RAM, carry chains, clocking, memory/SRAM macro mapping, and clock-enable conversion.
• Hands-on experience adapting ASIC RTL for FPGA, covering clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.
• Strong command of the full FPGA implementation flow (synthesis, place-and-route, timing analysis, and XDC/SDC constraint development) on large Xilinx and/or Intel (Altera) devices using Vivado and/or Quartus.
• Hardware bring-up and debug experience using in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug, alongside scripting proficiency in TCL and Python.
• BS or MS in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).

Nice to have

• Real-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages (ADC/DAC/PWM interfaces, plant/converter models).
• Understanding of digital power-conversion control and mixed-signal systems, including converter topologies, control loops, PWM/PFM, and magnetics.
• FPGA DSP implementation and real-time emulation of DSP datapaths (FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC, and folding/unfolding techniques).
• Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.
• Model-based design with Simulink and/or Xilinx System Generator.
• High-speed interface experience with JESD204B, PCIe, 1G/10G Ethernet, or Aurora.
• Embedded/microcontroller and firmware co-development experience in C/assembly, MATLAB, or C/C++.

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