Principal FPGA Emulation Engineer - Austin, United States

Originally posted 25 September 2026 by the employer.

About the role

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate mixed-signal power ASICs before silicon. These FPGA platforms are emulation vehicles, reproducing the target silicon functionally and achieving real-time performance for closed-loop power and DSP validation.

What you'll do

• Partner with silicon RTL and DSP architects to bring ASIC designs up on FPGA, advising on FPGA-ability.
• Adapt ASIC RTL for FPGA emulation while preserving functional equivalence, handling clock-gating, memory/SRAM mapping, and tri-state/bus conversion.
• Map designs onto the FPGA fabric to fit and achieve emulation speed, steering resource inference, clocking, and pipelining.
• Build the real-time environment around the digital core, modeling or interfacing to analog and power stages.
• Develop deep pre-silicon debug and visibility, including logic analysis, waveform capture, and assertions.
• Define and improve the emulation methodology, RTL/FPGA-ability guidelines, flows, and automation (TCL/Python).
• Provide technical leadership, mentor engineers, and drive emulation and tooling decisions.

What you'll need

• Extensive FPGA design and implementation experience (10+ years), including FPGA prototyping or emulation of ASIC/SoC designs.
• Expert-level RTL design in SystemVerilog and/or VHDL, with familiarity working from ASIC-style RTL.
• Deep understanding of FPGA internal architecture and primitives, including DSP/multiplier slices, block and distributed RAM, and clocking.
• Hands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, reset schemes, and multi-clock/CDC handling.
• Strong command of the full FPGA implementation flow: synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) on Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus.
• Hardware bring-up and debug experience: in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug.
• Proficiency scripting for automation (TCL, Python).
• Demonstrated technical leadership: mentoring, reviews, and driving cross-team technical decisions.
• BS or MS in Electrical Engineering, Computer Engineering, or a related field.

Nice to have

• Real-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages (ADC/DAC/PWM interfaces, plant/converter models).
• Understanding of digital power-conversion control and mixed-signal systems: converter topologies, control loops, PWM/PFM, and magnetics.
• FPGA DSP implementation and real-time emulation of DSP datapaths: FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC.
• Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.
• Model-based design with Simulink and/or Xilinx System Generator.
• High-speed interface experience: JESD204B, PCIe, 1G/10G Ethernet, Aurora.
• ASIC design or tape-out exposure, including DFT/scan considerations in emulation.
• Embedded/microcontroller and firmware co-development experience (C/assembly); MATLAB, C/C++.