Principal Foundry Interface Engineer - Santa Clara, CA, United States
$169,470 - $242,360 USD yearly
Originally posted 18 September 2026 by the employer.
About the role
This role supports the Foundry technical interface for SiTime, leading yield improvement and managing yield excursions.
What you'll do
- Lead Foundry yield improvement through mitigation of systematic and parametric yield detractors.
- Manage Foundry yield excursion and implement Continuous Improvement Plans.
- Provide technical guidance on Foundry Fab transfer projects.
- Direct wafer lot progress, process skew splits, and DOE strategies during development.
- Support device performance analysis for mixed signal devices.
- Serve as technical liaison to the Foundries, communicating process health monitors to internal stakeholders.
What you'll need
- Master’s degree with 13+ years or PhD with 10+ years of industry experience in Semiconductor Process Integration, Device Engineering, or Wafer Yield Engineering.
- Proven track record in yield pareto construction, modeling, projection, and long-term yield roadmaps.
- Experience using PDF Exensio or other Big Data Analysis tools.
- Extensive experience collaborating with foundries.
- Experience in porting between fabs.
- Expertise in interpreting complex product data (inline, e-test, and SORT) to drive solutions.
- Deep knowledge of semiconductor wafer inline inspection methods and SORT programs.
- Deep knowledge of semiconductor device reliability.
- Well versed with DFM techniques and PFMEA.
- Experience in supporting semiconductor wafer fulfillment for products meeting Automotive AEC_Q100, ISO 26262 standards.
Nice to have
- Experience with AI/ML predictive modeling to improve projection accuracy for test chips and high-volume products, including correlation of inline process metrics with end-of-line yield and performance.
Skills: Foundry yield improvement, yield detractors, yield excursion, process integration, AEC_Q100
This role has been open 24 days — well below the 51-day median for Yield Engineering roles.
Yield Engineering · Yield Engineering
|
Open roles in category
218
|
Median days open
51 d
|
Median salary
$130k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiTime | All employers we track in this specialty (218 roles · 36 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 218 |
| Median days open | 24 d | 51 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $130k |
Skills observed across this category: Foundry yield improvement, yield detractors, yield excursion, process integration, AEC_Q100
Who's hiring in this category
- Micron Technology · 117 open roles · median 53 d
- Intel Corporation · 12 open roles · median 15 d
- GlobalFoundries · 10 open roles · median 185 d
- Skyworks · 7 open roles · median 67 d
- Qualcomm · 6 open roles · median 126 d
- STMicroelectronics · 6 open roles · median 42 d
How we counted: 218 open Yield Engineering (Yield Engineering) roles from 36 employers tracked in the SemiconductorJobs index, counted 13 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.