Principal Foundry Interface Design Engineer, HBM
Originally posted 16 September 2026 by the employer — open 2 days.
This role provides critical technology support for the design and development of advanced HBM DRAM products.
About the role
This role provides critical technology support for the design and development of advanced HBM DRAM products. Your work will directly impact performance, power efficiency, reliability, and long-term HBM roadmap success.
What you'll do
- Act as the primary technical interface between foundry partners and Micron design organizations.
- Drive closure of design-process gaps through collaborative engagement with foundry process teams.
- Perform HSPICE simulations for technology evaluation and design optimization.
- Plan and execute technology evaluation test chips.
- Evaluate foundry PDKs and IP collateral.
- Identify and implement AI-enabled workflows, automation opportunities, and knowledge-management practices.
What you'll need
- BS, MS, or PhD or equivalent experience in Electrical Engineering, Computer Engineering, or related field.
- 6+ years of semiconductor industry experience with a solid grasp of advanced semiconductor technology development.
- Strong understanding of advanced CMOS technology nodes, FinFET devices, and process integration.
- Hands-on experience with HSPICE simulations, Device characterization, Standard cell benchmarking, PPA analysis, Parasitic extraction, and physical verification.
- Experience in driving AI-enabled engineering practices and automation to improve efficiency of DTCO analysis, foundry collateral evaluation, PDK enablement, benchmarking, and knowledge sharing.
Nice to have
- Experience working directly with foundries such as TSMC, Samsung, Intel Foundry Services, or GlobalFoundries.
- Experience with memory products including DRAM, HBM, or SRAM.
- Knowledge of TSV technologies, Advanced packaging, Reliability modeling and aging simulations, Advanced BEOL technologies, PDK development and validation.
- Ability to utilize AI tools to summarize, analyze, and extract insights from PDK documentation, Design Rule Manuals (DRM), Reliability reports, Foundry collateral, and Silicon characterization data.
- Experience leading technology pathfinding and node selection activities.
This role has been open 2 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
85 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (671 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 671 |
| Open roles in the wider Physical Implementation family | 67 | 1371 · 106 employers |
| Median days open | 120 d | 85 d (+35 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Who's hiring in this category
- Cadence Design Systems · 168 open roles · median 147 d
- Synopsys · 55 open roles · median 58 d
- NVIDIA · 47 open roles · median 71 d
- Micron Technology (this employer) · 36 open roles · median 117 d
- Qualcomm · 34 open roles · median 71 d
- Intel Corporation · 29 open roles · median 24 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.